Testable high count counter
AssigneeLucent Technologies Inc.
InventorsSonali Bagchi, Jalil Fadavi-Ardekani, Kenneth Daniel Fitch, Daisuke Takise
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Abstract
An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR) having n bit positions is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate that couples selected bits back to the input of the register, in order to implement a 2.sup.n -1 counter. Combinatorial logic circuitry is included to test the counter in significantly less than 2.sup.n -1 clock cycles. This allows for implementing a testable "watchdog timer" that may be used to detect software runaway conditions in microprocessor systems, among other uses.
Claims12
An integrated circuit comprising a shift register having n bit locations and having a data input for receiving a data signal, a set input for receiving a set signal, and a clock input for receiving a clock signal;
- and further comprising feedback circuitry for feeding back a data signal to said data input when a given pattern of bits is located in said shift register;
- characterized in that said integrated circuit further comprises first combinatorial logic circuitry having n inputs connected to said n bit locations, and having an output to indicate that a desired test pattern has been achieved when each bit of the shift register has made all possible state transitions in a number of clock cycles less than 2.sup.n -1;
- and further characterized in that said integrated circuit further comprises second combinatorial logic circuitry having n inputs connected to said n bit locations, and having an output to indicate when a count of 2.sup.n -1 clock cycles has been achieved.
A computer system having a watchdog timer for indicating the occurrence of a software runaway situation, said watchdog timer including a counter comprising:
- a shift register having n bit locations and having a data input for receiving a data signal, a set input for receiving a set signal, and a clock input for receiving a clock signal;
- and further comprising feedback circuitry for feeding back a data signal to said data input when a given pattern of bits is located in said shift register;
- characterized in that said watchdog timer further comprises first combinatorial logic circuitry having n inputs connected to said n bit locations, and having a test output to indicate that a desired test pattern has been achieved when each bit of the shift register has made all possible state transitions in a number of clock cycles less than 2.sup.n -1;
- and further characterized in that said watchdog timer further comprises second combinatorial logic circuitry having n inputs connected to said n bit locations, and having a reset output to indicate when a count of 2.sup.n -1 clock cycles has been achieved, with said reset output being coupled to reset circuitry.
A method for resetting a computer system upon the occurrence of a software runaway situation, comprising the step of counting a clock signal by means of a counter, characterized in that said counting is accomplished by steps comprising:
- shifting data into a shift register having n bit locations via a data input under the control of a clock signal received via a clock input;
- and feeding back a data signal to said data input when a given pattern of bits is located in said shift register, whereby a 2.sup.n -1 counter is implemented for resetting said computer system;
- and wherein said counter comprises test circuitry that logically combines the data in the n bit positions of the counter to form an output signal that indicates that a desired pattern has been achieved when each bit of the shift register has made all possible state transitions in a number of clock cycles less than 2.sup.n -1.
Dependencies are inferred from the claim text.