US 5,694,440 A · Data synchronizer lock detector and method of operation thereof

Abstract

In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.

Claims14

Dependent claims

A method of generating a lock detect signal in a data synchronizer lock detector having a delay circuit responsive to a demodulated sequence of data symbols, a summing circuit, a sampler, and a signal processor, the method comprising the steps of:

providing a delayed demodulated sequence of data symbols:
responding to said delayed demodulated sequence of data symbols and to said demodulated sequence of data symbols and generating a difference signal;
responding to said difference signal and generating an on-time difference signal and a delayed-time difference signal;
and
applying a non-linear function to said on-time difference signal and to said delayed-time difference signal to produce a lock indication.

2 more elements

A method of generating a lock detect signal in a data synchronizer lock detector having first and second delay circuits, first, second, and third summing circuits, first and second samplers, first and second signal processors, and a comparator, the method comprising the steps of:

(a) providing a delayed demodulated sequence I of data symbols for a real component by responding to a demodulated sequence of data symbols comprising said real component;
(b) providing a delayed demodulated sequence Q of data symbols for an imaginary component by responding to a demodulated sequence of data symbols comprising said imaginary component:
(c) responding to said delayed demodulated sequence I and to said demodulated sequence I and generating a first difference signal;
(d) responding to said delayed demodulated sequence Q and to said demodulated sequence Q and generating a second difference signal;
(e) responding to said first difference signal and generating an on-time first difference signal and a delayed-time first difference signal;
(f) responding to said second difference signal and generating an on-time second difference signal and a delayed-time second difference signal;
(g) applying a non-linear function to said on-time first difference signal and to said delayed-time first difference signal to produce a lock indication for said real component;
(h) applying a non-linear function to said on-time second difference signal and to said delayed-time second difference signal to produce a lock indication for said imaginary component;
(i) responding to said lock indications and generating a sum signal;
and
(j) responding to said sum signal and to a threshold value and generating a lock output if said sum signal differs from said threshold value.

8 more elements

A data synchronizer lock detector comprising:

first and second delay circuits, said first delay circuit responsive to a demodulated sequence of data symbols comprising a real component and providing a delayed demodulated sequence I of data symbols for said real component, and said second delay circuit responsive to a demodulated sequence of data symbols comprising an imaginary component and providing a delayed demodulated sequence Q of data symbols for said imaginary component;
first and second summing circuits, said first summing circuit being responsive to said delayed demodulated sequence I and to said demodulated sequence I and generating a first difference signal, and said second summing circuit being responsive to said delayed demodulated sequence Q and to said demodulated sequence Q and generating a second difference signal;
first and second samplers, said first sampler being responsive to said first difference signal and generating an on-time first difference signal and a delayed-time first difference signal, and said second sampler being responsive to said second difference signal and generating an on-time second difference signal and a delayed-time second difference signal;
a signal processor, said signal processor applying a non-linear function to said on-time first difference signal and to said delayed-time first difference signal to produce a lock indication for said real component, and said signal processor applying a non-linear function to said on-time second difference signal and to said delayed-time second difference signal to produce a lock indication for said imaginary component;
a third summing circuit, said third summing circuit being responsive to said lock indications and generating a sum signal;
and
a comparator responsive to said sum signal and to a threshold value and generating a lock output if said sum signal differs from said threshold value.

4 more elements

Dependencies are inferred from the claim text.

Data synchronizer lock detector and method of operation thereof

Life of this patent

Data synchronizer lock detector and method of operation thereof

Life of this patent

Abstract

Claims14