Parallel associative processor formed from modified dram
AssigneeBoard of Regents, The University of Texas System
InventorG. Jack Lipovski
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Abstract
A parallel associative processor is formed from a DRAM circuit whose storage positions are organized into words, which are further subdivided into columns. Each column is associated with a sense amplifier, which is used to perform data refreshing. Comparators are coupled to the sense amplifiers to permit logical operations, including comparisions with external data placed on a bus, to be performed on data addressed and read from the storage positions, including during refresh operations. A latch or flip-flop with control inputs is associated with each word, to hold a match or mismatch signal identifying, in parallel for each word, the results of the logical operations.
Claims20
A processor formed from a dynamic semiconductor memory chip supporting:
- (a) a multitude of single-bit storage cells distributed among a plurality of word cells;
- (b) wherein the bit cells of each word cell are arranged in a plurality of columns, each comprised of a plurality of bit cells;
- (c) a plurality of sense amplifiers, each of said columns being associated with one of said sense amplifiers;
- (d) wherein each of the sense amplifiers can be electrically coupled to any bit cell in any column with which that sense amplifier is associated;
- (e) an addressing circuit coupled to each of the sense amplifiers associated with columns of at least one word cell;
- (f) wherein the addressing circuit controls the coupling of the sense amplifiers to the bit cells of any row extending across the associated columns of the word cell;
- and
- (g) an input/output bus that extends onto the chip and is coupled to the sense amplifiers associated with each of the word cells;
- wherein the improvement comprises further integrating on the chip:
- (h) a plurality of comparison circuits, each of which (i) is associated with one of the word cells, (ii) is coupled to the sense amplifiers associated with that word cell, (iii) has an output line, and (iv) is structured to compare a selected common comparand on the chip's input/output bus with a row of bits in the word cell amplified by said sense amplifiers and to generate an electrical signal on said output line when the comparand does not match the bits amplified from the bit cells in the row;
- and (i) a plurality of match flip-flops, each of which is associated with one of the word cells and each responsive to set and clear control inputs, and wherein the clear input for each word is coupled to the output line extending from the comparison circuit for the same word.
A processor formed from a single-chip, dynamic data storage device including:
- (a) means for storing on the chip a multitude of bits divided among a plurality of logical words, arranged in an array having multiple columns and rows, wherein the bits of each word are grouped into a plurality of multi-bit columns;
- (b) sense amplifier means, integrated on the chip, for amplifying all bits in a row;
- and
- (c) addressing means, coupled to the sense amplifier means, for addressing any row of the columns by controlling the coupling between the sense amplifier means and the bits in the row of the columns;
- wherein the improvement comprises further integrating on the chip:
- (d) comparison means, coupled to the sense amplifier means of each word, for comparing a selected comparand provided to the chip with bits of a row amplified by said sense amplifier means, and for generating an electrical signal on an output line for each word when the comparand does not match the amplified bits;
- and
- (e) latch means for holding a match signal for each word, which latch means is responsive to set and clear control inputs, each clear input being coupled to the output line for the same word.
Forming a processor from a single-chip, dynamic data storage device including:
- (a) means for storing on the chip a multitude of bits divided among a plurality of logical words, arranged in an array having multiple columns and rows, wherein the bits of each word are grouped into a plurality of multi-bit columns;
- (b) sense amplifier means, integrated on the chip, for amplifying all bits in a row;
- and
- (c) addressing means, coupled to the sense amplifier means, for addressing any row of the columns by controlling the coupling between the sense amplifier means and the bits in the row of the columns;
- comprising the step of further integrating on the chip:
- (d) comparison means, coupled to the sense amplifier means of each word, for comparing a selected comparand provided to the chip with bits of a row amplified by said sense amplifier means, and for generating an electrical signal on an output line for each word when the comparand does not match the amplified bits;
- and
- (e) latch means for holding a match signal for each word, which latch means is responsive to set and clear control inputs, each clear input being coupled to the output line for the same word. .
Dependencies are inferred from the claim text.