Encoder and decoder of an error correcting code

An encoder for encoding communication data, the communication data comprising data words each having n bits (n being a positive integer), the encoder receiving 2n parallel bits, the 2n parallel bits comprising a first n bit word and a second n bit word, the encoder comprising:

• a logic gate for generating a logic signal;
• a 2n division pattern circuit for generating a first division pattern;
• an n division pattern circuit for generating a second division pattern;
• the logic gate being connected to receive the first n bit word and the first division pattern;
• the 2n division pattern circuit being connected to receive the logic signal and the second n bit word;
• the n division pattern circuit being connected to receive the logic signal;
• and
• a selector connected to the 2n division pattern circuit and the n division pattern circuit for selecting the first division pattern or the second division pattern.

A decoder for decoding communication data, the communication data comprising data words each having n bits (n being a positive integer), the decoder receiving 2n parallel bits, the 2n parallel bits comprising a first n bit word and a second n bit word, the decoder comprising:

• a first logic gate for generating a first logic signal;
• a second logic gate for generating a second logic signal;
• a 2n division pattern circuit for generating a first division pattern;
• an n division pattern circuit for generating a second division pattern;
• the first logic gate being connected to receive the first n bit word and the first division pattern;
• the second logic gate being connected to receive the second n bit word and the second division pattern;
• the 2n division pattern circuit being connected to receive the first logic signal and the second n bit word;
• the n division pattern circuit being connected to receive the first logic signal;
• a first detector circuit for receiving the first logic signal and for determining whether an error exists in the communication data when an error correcting code appears in the first n bit word;
• and
• a second detector circuit for receiving the second logic signal and for determining whether an error exists in the communication data when an error correcting code appears in the second n bit word.

A decoder for decoding communication data that includes an n bit error correcting code, comprising:

• a data input bus for inputting received communication data by 2n bits parallel in each cycle;
• a first switch circuit for passing inputted n bit data which are n more significant bits of the 2n bit data from the data input bus when the n more significant bit data of the 2n bit data from the data input bus are the coded communication data;
• a second switch circuit for passing inputted n bit data which are n less significant bits of the 2n bit data from the data input bus when the n less significant bit data of the 2n bit data from the data input bus are the coded communication data;
• a first gate circuit for taking an exclusive OR of the n bit data from the first switch circuit and an n bit first division pattern;
• a first shift register for storing n bit data from the first gate circuit as n significant bit data and the n bit data from the second switch circuit as n less significant bit data and for outputting the stored 2n bit data in the next cycle;
• a first division pattern generating circuit for generating the n bit first division pattern from the 2n bit data from the first shift register;
• a second division pattern generating circuit for generating an n bit second division pattern from the n significant bit data of the 2n bit data from the first shift register;
• a second gate circuit for taking an exclusive OR of the n less significant bit data of the 2n bit data from the first shift register and the n bit second division pattern;
• a first detecting circuit for detecting that the n significant bit data of the 2n bit data from the first shift register is equal to prescribed data which means that there is no error in the received coded data;
• and
• a second detecting circuit for detecting that the n bit data from the second gate circuit is equal to the prescribed data which means that there is no error in the received coded data.

An encoder for encoding communication data with an n bit error correcting code, comprising:

• a data input bus for inputting the header of the communication data by 2n bits parallel in each cycle;
• a first switch circuit for passing inputted n bit data which are n more significant bits of the 2n bit data from the data input bus when the n more significant bit data of the 2n bit data from the data input bus are the data which is to be coded;
• a second switch circuit for passing inputted n bit data which are n less significant bits of the 2n bit data from the data input bus when the n less significant bit data of the 2n bit data from the data input bus are the data which is to be coded;
• a first gate circuit for taking an exclusive OR with respect to the n bit data from the first switch circuit and an n bit first division pattern;
• a first division pattern generating circuit for generating the n bit first division pattern from the n bit data from the first gate circuit and the n bit data from the second switch circuit;
• a shift register for storing the n bit data from the first division pattern generating circuit and for outputting the stored n bit data in the next cycle;
• a second division pattern generating circuit for generating an n bit second division Pattern from n bits data from the first gate circuit;
• and
• a selector for selecting alternatively the n bit data from the shift register or the n bit data from the second division pattern generating circuit as the error correcting code.

An encoder for encoding communication data with an n bits error correcting code in a header, comprising:

• a data input bus for inputting the header of the communication data by 2n bits parallel in each cycle;
• a first switch circuit for passing inputted n bit data which are n more significant bits of the 2n bit data from the data input bus when the n more significant bit data of the 2n bit data from the data input bus are the data which is to be coded;
• a second switch circuit for passing inputted n bit data which are n less significant bits of the 2n bit data from the data input bus when the n less significant bit data of the 2n bit data from the data input bus are the data which is to be coded;
• a first gate circuit for taking an exclusive OR with respect to the n bit data from the first switch circuit and an n bit first division pattern;
• a shift register for storing the n bit data from the first gate circuit as n more significant bit data and the n bit data from the second switch circuit as n less significant bit data and for outputting the stored 2n bit data in the next cycle;
• a first division pattern generating circuit for generating the n bit first division pattern from the 2n bit data from the shift register;
• a second division pattern generating circuit for generating an n bit second division pattern from n more significant bit data of the 2n bit data from the shift register;
• a second gate circuit for taking an exclusive OR of the n less significant bit data of the 2n bit data from the shift register and the n bit second division pattern;
• and
• a selector for selecting alternatively the n significant bits of the 2n bit data from the shift register or the n bit data from the second gate circuit as the error correcting code.