System and method for sequential vector compaction in the presence of multiple three-state busses

A system for generating compact sequences of test vectors for testing a computer generated circuit design, said system comprising:

• a CPU for
• (a) determining a first minimum set of primary input values to each three state bus in the circuit being tested, said primary input values being required to resolve said three state busses;
• (b) targeting a primary fault to be detected in said circuit design and generating a sequence to detect said primary fault, said sequence including a second set of primary inputs;
• (c) targeting a secondary fault to be detected in said circuit design and generating a sequence to detect said secondary fault, said sequence including said second set of primary inputs;
• (d) attempting to satisfy all of said three-state busses with said first minimum set of primary inputs;
• (e) substituting said second set of primary inputs for said recorded first minimum set of primary inputs if all of said three-state busses can be satisfied with said first minimum set of primary inputs,
• memory unit for recording said first minimum set of primary inputs and a time value associated with each input, each of said time values indicating a relative place in time when said primary input is applied to one of said three-state busses.