US 5,694,401 AGranted

Fault isolation using pseudo-random scan

AssigneeTandem Computers Incorporated

InventorWalter E. Gibson

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Abstract

A digital system, comprising a plurality of integrated circuits that are designed to be scannable for pseudo-random scan testing. Testing begins and proceeds in normal binary-tree fashion, subjecting the system to a pseudo-random scan test and developing from that test a signature that is compared to a standard signature. If the comparison is unequal, portions of the system are subjected to pseudo-random scan testing, in normal binary-tree fashion, until the integrated circuit level is reached whereat a final mis-compare for the signature developed for a integrated circuit is obtained. Then, each bit position of the scan for such integrated circuit is classified according to the source of data for its primary input, and pseudo-random scan testing conducted to extract signatures for each such classified source. When a bad signature is reached, after comparing to standard signatures, the fault has been isolated to the classified source.

Claims6

Dependent claims

A method of fault isolation by pseudo-random scan-testing a digital system having a number of integrated circuits, each of the integrated circuits including a plurality of logic elements each operating in a first mode as a one-bit storage element having an input receiving data from a corresponding source and, in response to test signals, in a second mode to form one or more scan shift registers, each of the scan shift registers having a scan data input and a scan data output permitting pseudo-random testing to be performed, the method comprising the steps of:

classifying each of the one-bit storage elements of each of the number of integrated circuits according to the corresponding source applying data to the input of such one-bit storage element when operating in the first mode;
asserting the test signals;
applying pseudo-random scan data to the scan data input of each of the number of integrated circuits;
sequentially selecting data from the scan data output of each of the number of integrated circuits to obtain output scan data for comparison to a predetermined output scan data indicative of operability;
if the output scan data from one of the number of integrated circuits does not compare to the predetermined output scan data, applying again pseudo-random scan data to obtain scan data from one of the number of integrated circuits and selectively extracting portions of the scan data according to classification;
and
comparing the extracted portions to selected portions of the predetermined scan data to isolate a fault according to said classification.

4 more elements

A method for isolating faults in a digital system formed from at least two circuit groups each including a plurality of logic elements operating in a first mode as a one-bit storage element having a data source input and, in response to one or more test signals, in a second mode to form one or more scan shift registers, each of the scan shift registers having a scan data input and a scan data output permitting pseudo-random testing to be performed to obtain from the scan data output scan data, the method comprising the steps of:

classifying each bit position of the scan data according to data received by the logic element corresponding to said bit position;
providing a plurality of Golden Signatures, including a system Golden Signature indicative of proper operation of the digital system, a first group Golden Signature indicative of proper operation of a one of the two circuit groups, and a second Golden Signature indicative of proper operation of the other one of the two circuit groups;
subjecting the digital system to a pseudo-random test to obtain a system signature developed from scan data extracted from the scan shift registers;
comparing the system signature to the system Golden Signature and terminating the testing if the system signature and system Golden signature match;
subjecting the digital system again to the pseudo-random test and extracting first predetermined bit positions from the scan data corresponding to predetermined ones of the logic elements according to a first classification to obtain a first group signature from the scan data corresponding to the one of the two circuit groups, and terminating the test if the first group signature and the first Golden Signature do not match with an indication of the fault being isolated on the one circuit group;
and
subjecting the digital system yet again to the pseudo-random test and extracting second predetermined bit positions from the scan data corresponding to predetermined ones of the logic elements according to a second classification to obtain a second group signature from the scan data corresponding to the other of the two circuit groups to provide an indication of the fault being isolated in the other of the two circuit groups if the second group signature does not match the second Golden Signature.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/787,452Filed 22 Jan 1997 · continuation
Priority: 27 Jun 1994
Granted: 2 Dec 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 31/318544
Using scanning techniques, e.g. LSSD, Boundary Scan, JTAG: scanning methods, algorithms and patterns
G01R 31/318385
Generation of test inputs, e.g. test vectors, patterns or sequences: random or pseudo-random test pattern
G06F 2201/83
Indexing scheme relating to error detection, to error correction, and to monitoring: the solution involving signatures
G01R
Measuring electric variables