Checking data integrity in buffered data transmission

Abstract

Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the data read out for parity in a parity checker (100). The invention may be used in a buffer memory (50) between two asynchronously timed buses.

Dependencies are inferred from the claim text.