A semiconductor memory device comprising:
- a memory cell array having first and second data input/output terminals
- and a plurality of memory cells arranged in a row direction and column direction in which, during a selected state, data in a mutually complementary level relation are written from the first and second data input/output terminals and stored, and stored data are read out;
- a plurality of word lines provided corresponding to each row of said plurality of memory cells which, when at a selected level, place a corresponding row of memory cells in a selected state;
- a plurality of bit line pairs provided corresponding to each column of said plurality of memory cells made up of first bit lines that connect first data input/output terminals and second bit lines that connect second data input/output terminals of corresponding columns of memory cells;
- a row address decoder that places at a selected level a prescribed word line among said plurality of word lines in accordance with row address signals when a word line enable signal is at an active level;
- a plurality of dummy memory cells provided at the end of each of said plurality of word lines most remote from said row address decoder, which have first and second data output terminals, which store data that are of fixed levels and in a mutually complementary level relation and, when in a selected state, which read these data from said first and second data output terminals;
- a dummy bit line pair made up of a first dummy bit line that connects to first data output terminals and a second dummy bit line that connects to second data output terminals of said plurality of dummy memory cells;
- a precharge circuit that precharges said plurality of bit line pairs and dummy bit line pair to a prescribed potential in response to an active level of a precharge control signal;
- a column selection circuit that selects a prescribed bit line pair among said plurality of bit line pairs in accordance with a column address signal;
- an amplification circuit that amplifies and outputs data of a bit line pair selected by said column selection circuit in response to an active level of a sense amplification enable signal;
- an output data latch circuit that latches and outputs output data of said amplification circuit in response to an active level of a data latch signal;
- a dummy amplification circuit that amplifies data of said dummy bit line pair in response to an active level of said sense amplification enable signal, and outputs the result as data of a level differing from the precharge potential of said dummy bit line pair;
- dummy amplification output precharge means that, before said sense amplification enable signal changes to an active level, precharges the level of the output terminal of said dummy amplification circuit to a level corresponding to the precharge potential of said dummy bit line pair;
- dummy amplification output delay means that delays data output timing of said dummy amplification circuit a prescribed, time interval from data output timing of said amplification circuit;
- an address transition, detection circuit that detects change in an address value of an address signal including said row address signal and column address signal and outputs an address transition detection signal;
- an internal control signal generation circuit that determines timing of level change to an active level of said word line enable signal, sense amplification enable signal, and data latch signal as well as timing of level change to an inactive level of said precharge control signal in response to said address transition detection signal, determines timing of level change to an inactive level of said word line enable signal, sense amplification enable signal, and data latch signal as well as timing of level change to an active level of said precharge control signal in response to timing of level change of output data of said dummy amplification circuit, and outputs said word line enable signal, sense amplification enable signal, data latch signal, and precharge control signal.