Memory device with efficient redundancy using sense amplifiers
AssigneeMicron Technology, Inc.
InventorsHank H. Lim, Brian Higgins
Life of this patent
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Abstract
A memory device is described which has memory storage cells coupled to data bit lines. Sense amplifier circuits are provided to receive input from the data bit lines and produce an output in response thereto. The memory includes circuitry which shifts the input to the sense amplifiers. Data bit lines from a neighboring sense amplifier is shifted to another sense amplifier such that redundant memory storage cells and data bit lines can be substituted for defective ones.
Claims19
A memory device comprising:
- memory storage cells for storing data;
- a plurality of memory columns defined by a plurality of bit lines coupled to the memory storage cells;
- a plurality of sense amplifier circuits having multiple inputs coupled to the plurality of memory columns, the plurality of sense amplifier circuits each having an output;
- and
- select circuitry connected to the plurality of sense amplifier circuits to couple one of the multiple inputs of each of the plurality of sense amplifier circuits to the output of the plurality of sense amplifier circuits.
A memory device comprising:
- a plurality of memory cells;
- a first pair of data communication bit lines;
- a second pair of data communication bit lines;
- addressing circuitry for selectively coupling the plurality of memory cells to the first and second pair of data communication bit lines;
- a first sense amplifier circuit coupled to the first and second pair of data communication bit lines for producing an output in response to the first pair of data communication bit lines;
- and
- select circuitry connected to the first sense amplifier circuit for enabling the first sense amplifier circuit to produce the output in response to the second pair of data communication bit lines.
A method of providing redundancy in a memory device, the method comprising the steps of:
- disabling a sense amplifier circuit associated with a first plurality of memory cells from producing an output in response to the first plurality of memory cells;
- and
- enabling the sense amplifier circuit associated with the first plurality of memory cells to produce the output in response to a plurality of redundant memory cells.
A static random access memory comprising:
- a memory array of static memory cells arranged in rows and columns;
- differential bit line pairs coupled to the static memory cell to define the columns of the memory array;
- two-stage sense amplifier circuits, each of the two-stage sense amplifier circuits having a first stage receiving data from one of the differential bit line pairs, and a second stage coupled to a data communication input/output;
- and
- select circuitry connected to the second stage of the two-stage sense amplifier circuits for operating the second stage amplifier circuits in either a first or second mode, wherein the first mode the second stage of one of the two-stage sense amplifier circuits produces an output in response to data received from the first stage of the one of the two-stage sense amplifier circuits, and wherein the second mode the second stage of one of the two-stage sense amplifier circuits produces an output in response to data received from the first stage of another one of the two-stage sense amplifier circuits.
Dependencies are inferred from the claim text.