Reading circuit for memory cell devices having a low supply voltage
AssigneeSGS-Thomson Microelectronics S.A.
InventorsCristiano Calligaro, Roberto Gastaldi, Nicola Telecco, Guido Torelli
Life of this patent
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Abstract
A device for reading memory cells, wherein the device contains two branches, wherein each branch comprises, connected in cascade, an electronic switch, an active element reactively connected to the active element of the other branch, so as to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element. A microswitch connects the two branches together is inserted between the two active elements.
Claims29
A reading circuit with a differential structure for reading memory cells comprising:
- two branches connected to a reference potential, wherein each branch includes components connected together in a cascade arrangement, wherein the components include an electronic switch and an active element which is connected in a feedback loop to the active element of the other branch, so as to form a voltage amplifier therewith;
- wherein the two branches are connected together by means of a microswitch which is inserted between the two active elements;
- and
- wherein a control terminal of the active element of one branch is electrically connected to a selection bit line of memory cell as to create a current path to said memory cell and a control terminal of the active element of another branch is electrically connected to a reference bit line of a memory cell so as to create a current path to said memory cell.
A memory device comprising:
- first and second bit lines;
- and
- a reading circuit, wherein said reading circuit includes a differential structure comprising two branches connected to a reference potential, wherein each branch includes components connected together in a cascade arrangement, wherein the components include an electronic switch and an active element which is connected in a feedback loop to the active element of the other branch, so as to form a voltage amplifier therewith, and wherein the two branches are connected together by means of a microswitch which is inserted between the two active elements, and a control terminal of an active element of one of said two branches electrically connects to the first bit line, and a control terminal of an active element of another of said two branches electrically connects to the second bit line.
A method of sensing a logic value stored in a selected memory cell, using a current sensing circuit containing first and second sensing branches, wherein a control terminal of an active element of the first sensing branch is electrically connected to a reference memory cell and the a control terminal of an active element of the second sensing branch is electrically connected to said selected memory cell, comprising the steps of:
- loading said reference memory cell with a predetermined logic value;
- pre-loading said first and second sensing branches with a predetermined potential;
- equalizing the potential between said first and second sensing branches within said sensing circuit by temporarily coupling said first and second sensing branches;
- providing current to said current sensing circuit;
- sensing current flow within said first and second sensing branches, wherein said current flows reflect a relationship between the predetermined logic value stored in said reference memory cell and a logic value stored in said selected memory cell.
A circuit for reading a logic value in a memory comprising:
- a reference memory cell;
- first and second sensing transistors, wherein a gate of said second sensing transistor is electrically connected to a selected memory cell and is also connected to a drain of said first sensing transistor, forming a first sense node;
- and a gate of said first sensing transistor is electrically connected to said reference memory cell and is also connected to a drain of said second sensing transistor, forming a second sense node;
- an activator circuit connected to sources of said first and second sensing transistors;
- a preloading circuit connected to said first and second sense nodes;
- an equalization circuit connected to between said first and second sense nodes;
- a clocking circuit connected to said activator circuit and connected to said equalization circuit.
Dependencies are inferred from the claim text.