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US 5,694,361 AGranted
Output circuit
OwnerToshiya Uchidainventor
Life of this patent
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OwnerToshiya Uchidainventor
Estimating the term…
The turn-on time of an output transistor is minimized to suppress the average value of the load current, and the load is electrically charged with an intermediate potential prior to outputting data to suppress the instantaneous value of the load current. The output circuit holds the load in an open state when a predetermined reset signal has a first logic level, and drives the load from a high-potential side power source or a low-potential side power source depending on the logic level of the output data when said predetermined reset signal changes to a second logic level, wherein the timing at which the reset signal changes from the first logic to the second logic is delayed at least until the logic level of the output data has settled. Furthermore, the load is driven at an intermediate potential between the high-potential side power source voltage, and the low-potential side power source voltage and is then driven on the high-potential side power source or the low-potential side power source depending on the logic level of the output data.
An output circuit which holds a load in an open state when a first reset signal has a first logic level, and drives the load from a first power source of a high-potential side or a second power source of a low-potential side depending on a logic level of a signal input to said output circuit when said first reset signal changes to a second logic level, comprising:
An output circuit which holds a load in an open state when a first reset signal has a first logic level, and drives the load from one of a first power source having a high-potential level and a second power source having a low-potential level depending on a logic level of a signal input to said output circuit when said first reset signal changes to a second logic level, said circuit comprising a driving means for driving said load for a predetermined period of time, at a predetermined constant intermediate potential level, said predetermined period being determined from a first timing at which said first reset signal changes from said first logic level to said second logic level to a second timing at which a second reset signal is changed, and said predetermined intermediate potential level being set at the level between potential levels output from a third power source having a high potential and a fourth power source having a low potential.
Dependencies are inferred from the claim text.