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US 5,694,359 AGranted
Flash memory device
AssigneeHyundai Electronics Industries Co., Ltd.
InventorJoo Weon Park
Life of this patent
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Abstract
The present invention relates to a flash memory cell device having a repair circuit for replacing a fail cell of main memory cell arrays with a spare cell. The flash memory device according to the present invention comprises a main memory cell array, a redundancy cell block, a redundancy row decoder, a row decoder, a column decoder, a flag bit cell block, a flag cell transfer gate, a main sense amplifier and a flag sense amplifier.
Claims6
A flash memory device comprising:
- a main cell array having a plurality of word lines and a plurality of bit lines;
- a column decoder for selecting any one of said bit lines;
- a row decoder for selecting any one of said word lines;
- a redundancy cell block connected between said bit lines and a plurality of spare word lines;
- a flag bit cell block coupled to said word lines, for storing whether any one word line of said word lines is failed or not;
- a flag sense amplifier coupled to a dummy bit line connected to a reference cell and said flag bit cell block;
- a redundancy row decoder for selecting said spare word lines in response to an output signal of the flag sense amplifier;
- and
- a main sense amplifier coupled to said dummy bit line and said column decoder.
6 more elements
A flash memory device comprising:
- a main cell array having a plurality of word lines and a plurality of bit lines;
- a column decoder for selecting any one of said bit lines;
- a row decoder for selecting any one of said word lines;
- a redundancy cell block connected between said word lines and a plurality of spare bit lines;
- a flag bit cell block coupled to said column decoder, for storing whether any one bit line of said bit lines is failed or not;
- a flag sense amplifier coupled to a dummy bit line which is connected to a reference cell and said flag bit cell block;
- a redundancy column decoder for selecting said spare bit lines in response to an output signal of said flag sense amplifier;
- and
- a main sense amplifier coupled to said dummy bit line and said column decoder.
6 more elements
Dependencies are inferred from the claim text.