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AssigneesHitachi, Ltd., Hitachi Device Engineering Co., Ltd.
InventorsTakayuki Kawahara, Yusuke Jyouno, Syunichi Saeki, Naoki Miyamoto, Katsutaka Kimura
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This invention provides a nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing the word line, and a plurality of memory cells including MOS transistors. Each of control gates of the MOS transistors are coupled to the word line and each of drains thereof are coupled to the bit lines, respectively. Each of the MOS transistors also has a floating gate. Further, the non-volatile semiconductor memory device comprises latch circuits, first switches, a sense amplifier coupled to the plurality of bit lines in common, and second switches. The latch circuits are coupled to the plurality of bit lines through the first switches which are coupled between the plurality of bit lines and the latch circuits, respectively. The second switches are respectively coupled between the plurality of bit lines and the sense amplifier, thereby coupling the sense amplifier to the bit lines. Each of the plurality of first switches includes a MOS transistor whose source-drain path is between a corresponding one of the plurality of bit lines and a corresponding one of the latch circuits, respectively. When data is to be read from a memory cell selected out of the plurality of memory cells, the plurality of first switches are turned off and one of the second switches between the selected memory cell and the sense amplifier is turned on.
A nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing said word line, and a plurality of memory cells including MOS transistors whose control gates are coupled to said word line and whose drains are coupled to said bit lines respectively, each of the MOS transistors having a floating gate, said non-volatile semiconductor memory device comprising:
A nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing said word line, and a plurality of memory cells including MOS transistors whose control gates are coupled to said word line and whose drains are coupled to said plurality of bit lines respectively, each of the MOS transistors having a floating gate, said non-volatile semiconductor memory device comprising:
A nonvolatile semiconductor memory device having memory cells including MOS transistors each having a floating gate and a control gate, each of said MOS transistors having a drain coupled to a bit line, comprising:
A nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing said word line, and a plurality of memory cells including MOS transistors whose control gates are coupled to said word line and whose drains are coupled to said bit lines, respectively, each of the MOS transistors having a floating gate, said non-volatile semiconductor memory device comprising:
Dependencies are inferred from the claim text.