Nonvolatile semiconductor memory device for storing multi-value data
AssigneeKabushiki Kaisha Toshiba
InventorSeiichi Mori
Life of this patent
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Abstract
Each of the cell transistors which constitute an EEPROM is set one of the first to fourth threshold voltages, to store one of four different data items. The first and fourth threshold voltages are the lowest and the highest of the four, respectively, and the second threshold voltage is lower than the third threshold voltage. Each cell transistor is set at a neutral threshold voltage when the charge-accumulating layer accumulates no charge. The neutral threshold voltage is higher than the second threshold voltage and lower than the third threshold voltage. The difference between the neutral threshold voltage and one of the four threshold voltages is so small that the self-field of the cell transistor has a low intensity.
Claims33
A nonvolatile semiconductor memory comprising:
- a semiconductor substrate of a first conductivity type;
- and
- a MOS transistor having a charge-accumulating layer provided on said semiconductor substrate and set at one of first to fourth threshold voltages in accordance with a charge applied to said charge-accumulating layer, thereby to store multi-value data,
- wherein said MOS transistor is set at a neutral threshold voltage when said charge-accumulating layer accumulates no charge, and the neutral threshold voltage is higher than the second threshold voltage which is higher than the first threshold voltage and the neutral threshold voltage is lower than the third threshold voltage which is lower than the fourth threshold voltage,
- wherein a difference between the neutral threshold voltage and the first threshold voltage is equal to a difference between the neutral threshold voltage and the fourth threshold voltage.
A nonvolatile semiconductor memory comprising:
- a semiconductor substrate of a first conductivity type;
- and
- a MOS transistor having a charge-accumulating layer provided on said semiconductor substrate and set at one of a plurality of threshold voltages in accordance with a charge applied to said charge accumulating layer, thereby to store multi-value data,
- wherein the threshold voltages are divided into two groups each consisting of the same number of threshold voltages, the threshold voltages of the first group being lower than a neutral threshold voltage of said MOS transistor, and the threshold voltages of the second group being higher than the neutral threshold voltage,
- wherein a difference between the neutral threshold voltage and one of the threshold voltages of the first group is equal to a difference between the neutral threshold voltage and one of the threshold voltages of the second group.
A nonvolatile semiconductor memory comprising:
- a first memory-cell array comprising a plurality of memory cells for storing multi-value data;
- a second memory-cell array comprising random-access memory cells for storing the multi-value data read from said first memory-cell array;
- and
- a control circuit connected to said first and second memory-cell arrays, for reading data stored in said second memory-cell array.
A method for assigning first to fourth threshold voltage ranges of multi-bit data stored in a MIS transistor with a floating gate with a neutral threshold voltage comprising steps of:
- assigning the first threshold voltage range above the neutral threshold voltage;
- assigning the second threshold voltage range above the neutral threshold voltage;
- assigning the third threshold voltage range below the neutral threshold voltage;
- and assigning the fourth threshold voltage range below the neutral threshold voltage,
- wherein a difference between the neutral threshold voltage and the first threshold voltage range is equal to a difference between the neutral threshold voltage and the fourth threshold voltage range.
A method for assigning a plurality of threshold voltage ranges of multi-bit data stored in a MIS transistor with a floating gate with a neutral threshold voltage comprising steps of:
- assigning a part of the threshold voltage ranges above the neutral threshold voltage;
- and
- assigning the rest of the threshold voltage ranges below the neutral threshold voltage,
- wherein a difference between the neutral threshold voltage and the highest of the threshold voltage ranges above the neutral threshold voltage is equal to a difference between the neutral threshold voltage and the lowest of the threshold voltage ranges below the neutral threshold voltage.
A method for storing and reading multi-bit data stored in a MIS transistor with a floating gate with a certain neutral threshold voltage, comprising steps of:
- assigning a first threshold voltage range above the neutral threshold voltage;
- assigning a second threshold voltage range above the neutral threshold voltage and below the first threshold voltage range;
- assigning a third threshold voltage range below the neutral threshold voltage;
- assigning a fourth threshold voltage range below the third threshold voltage;
- applying a first control voltage at a control gate of the MIS transistor, the first control voltage being between the first and the second threshold voltage ranges;
- applying a second control voltage at said control gate, the second control voltage being between the second and the third threshold voltage ranges;
- and
- applying a third control voltage at said control gate, the third control voltage being between the third and the fourth threshold voltage ranges.
A method for storing and reading a multi-bit data stored using a MIS transistor with a floating gate with a certain neutral threshold voltage comprising steps of:
- assigning N (integer) threshold voltage ranges of the multi-bit data storage above the neutral threshold voltage;
- assigning M (integer) threshold voltage ranges of the multi-bit data storage below the neutral threshold voltage;
- and
- applying control voltages at a control gate of the MIS transistor N+M-1 times, each of the applied voltages being between two of the threshold voltage ranges,
- wherein N+M is larger than 2, and the threshold voltage ranges are not overlapping.
A nonvolatile semiconductor memory cell comprising a charge storing layer, said nonvolatile semiconductor memory cell having a neutral threshold voltage in the absence of a net charge on said charge storing layer and 2.sup.N+1 (N being a positive integer) programmable threshold voltage ranges each resulting from a respective level of charge being placed on said charge storing layer and each representing a respective data state, wherein the neutral threshold voltage is halfway between the highest and the lowest of the programmable threshold voltage ranges.
Dependencies are inferred from the claim text.