Non-volatile ferroelectric memory device equipped with reference voltage generator for exactly regulating reference voltage to the mid point between two logic level and method of reading out data bit therefrom

A non-volatile ferroelectric memory device comprising:

• a plurality of addressable memory cells each including a series combination of a first switching transistor and a storage capacitor for storing a data bit in one of first and second logic levels, said storage capacitor having a dielectric film of ferroelectric substance sandwiched between a first electrode and a second electrode so as to change a polarization status depending upon a potential between said first and second electrodes along a hysteresis loop;
• a plurality of bit line pairs selectively associated with said plurality of addressable memory cells, each of said plurality of bit line pairs including a first bit line and a second bit line to which input and output nodes of the first switching transistors of associated addressable memory cells are selectively connected;
• a plurality of plate lines selectively associated with said plurality of addressable memory cells, each of said plurality of plate lines being connected to the second electrodes of the storage capacitors of associated addressable memory cells;
• a plurality of word lines selectively connected to control nodes of the first switching transistors of said plurality of addressable memory cells, and selectively driven to an active level so that said first switching transistors of said associated addressable memory cells turn on for electrically connecting the first electrodes of the storage capacitors to the first bit lines or the second bit lines,
• said data bit in said first logic level stored in said storage capacitor of one of said plurality of memory cells supplying a large amount of electric charge from said first electrode through the associated first switching transistor to said first bit line of an associated bit line pair for generating a first potential level on said first bit line,
• said data bit in said second logic level stored in said storage capacitor of said one of said plurality of memory cells supplying a small amount of electric charge from said first electrode through the associated first switching transistor to said first bit line of said associated bit line pair for generating a second potential level on said first bit line;
• a reference voltage generator including a plurality of reference voltage sub-generators selectively associated with said plurality of bit line pairs, one of said reference voltage sub-generators associated with said associated bit line pair including
• a first dummy memory cell implemented by a series combination of a second switching transistor and a first dummy storage capacitor having a dielectric film of said ferroelectric substance sandwiched between third and fourth electrodes and storing a first dummy bit of said first logic level,
• a second dummy memory cell implemented by a series combination of a third switching transistor and a second dummy storage capacitor having a dielectric film of said ferroelectric substance sandwiched between fifth and sixth electrodes and storing a second dummy bit of said second logic level, and
• a capacitive means electrically connectable to said first dummy memory cell and said second dummy memory cell and having a capacitance approximately equal to a parasitic capacitance coupled to said second bit line,
• said first dummy storage capacitor and said second dummy storage capacitor supplying the total of said large amount of electric charge and said small amount of electric charge to the second bit line and said capacitive means so as to regulate said second bit line to a reference voltage level between said first potential level and said second potential level;
• and
• a plurality of sense amplifiers selectively connected to said plurality of bit line pairs, each of said plurality of sense amplifiers magnifying a potential difference between said first bit line and said second bit line of one of said plurality of bit line pairs.

A method of reading out a data bit from a memory cell for storing a data bit in a ferroelectric capacitor in the form of polarization status, comprising the steps of:

• a) equalizing a first bit line with a second bit line paired with said first bit line;
• b) selecting at least one memory cell for supplying first electric charge representative of a data bit of logic "1" level or second electric charge representative of a data bit of logic "0" level to said first bit line for producing a first potential level representative of said data bit of logic "1" level or a second potential level representative of said data bit of logic "0" level on said first bit line;
• c) supplying said first electric charge representative of a first dummy data bit and said second electric charge representative of a second dummy data bit from a first dummy ferroelectric capacitor and a second dummy ferroelectric capacitor to a capacitive means having a capacitance twice as large as a parasitic capacitance coupled to said second bit line for producing a reference voltage at an intermediate point between said first potential level and said second potential level on said second bit line;
• d) magnifying a potential difference between said first bit line and said second bit line for quickly discriminating the logic level of said data bit read out to said first bit line;
• and
• e) restoring said data bit, said first dummy data bit and said second dummy data bit to said at least one memory cell, said first dummy ferroelectric capacitor and said second dummy ferroelectric capacitor, respectively.