Semiconductor memory device having layout area of periphery of output pad reduced

A semiconductor memory device comprising:

• a semiconductor substrate,
• a plurality of memory cell arrays formed on said semiconductor substrate,
• a plurality of output pads corresponding to said plurality of memory cell arrays, and formed at predetermined intervals in a straight line at the center of said semiconductor substrate,
• a plurality of output control circuits formed on said semiconductor substrate corresponding to said plurality of memory cell arrays, each output control circuit for providing a readout data signal readout from a corresponding memory cell array and generating a predetermined control signal,
• a plurality of signal generation circuits formed on said semiconductor substrate at the center portion thereof corresponding to said plurality of memory cell arrays, each signal generation circuit responsive to said readout data signal provided from a corresponding output control circuit for generating a pair of data signals complementary to each other, and controlled in response to said control signal from said corresponding output control circuit,
• a plurality of signal line groups formed on said semiconductor substrate corresponding to said plurality of memory cell arrays, each signal line group including at least three signal lines connected between a corresponding output control circuit and a corresponding signal generation circuit for transmitting said readout data signal and said control signal,
• a plurality of output drivers formed on said semiconductor substrate corresponding to said plurality of memory cell arrays, each output driver arranged in the proximity of a corresponding output pad, and responsive to said pair of readout signals from a corresponding signal generation circuit for supplying data to a corresponding output pad, and
• a plurality of signal line pairs formed on said semiconductor substrate corresponding to said plurality of memory cell arrays, each signal line pair connected between a corresponding signal generation circuit and a corresponding output driver for transmitting said pair of data signals.