Low power parallel multiplier for complex numbers
AssigneeAmati Communications Corporation
InventorDebajyoti Pal
Life of this patent
Estimating the term…
Abstract
A high speed, low power parallel multiplier is described. The parallel multiplier includes specialized hardware circuitry designed to perform complex multiplication operations at high speeds. The parallel multiplier requires significantly less die area than conventionally required, which results in reduced manufacturing costs and reduced power consumption.
Claims18
A parallel multiplier circuit for multiplication of fast and second complex numbers, said multiplier circuit comprising:
- a first multiplier for multiplying a first coefficient with a first variable to produce a first multiplication result;
- a first adder for adding the first variable with a second variable to produce a first sum;
- a second multiplier for multiplying a second coefficient with the first sum to produce a second multiplication result;
- a third multiplier for multiplying a third coefficient with the second variable to produce a third multiplication result;
- a second adder/subtractor for subtracting the second multiplication result from the first multiplication result to produce a first output;
- and
- a third adder for adding the second multiplication result to the third multiplication result to produce a second output.
A parallel multiplier circuit for multiply a first complex number (a+jb) by a second complex number (x.sub.0 +jx.sub.1) to produce a complex result (Y.sub.0 +jy.sub.0, said multiplier circuit receiving as inputs variables x.sub.0 and x.sub.1 and coefficients of A, B and C, where A=a+b, B=b, and C=a-b, said multiplier circuit comprising:
- a first adder for adding x.sub.0 and x.sub.1 as a first sum (x.sub.0 +x.sub.1)
- a first multiplier for multiplying A with x.sub.0 to produce a first multiplication result (Ax.sub.0);
- a second multiplier for multiplying B with the first sum (x.sub.0 +x.sub.1) to produce a second multiplication result B(x.sub.0 +x.sub.1);
- a third multiplier for multiplying C with x.sub.1 to produce a third multiplication result (Cx.sub.1);
- a second adder/subtractor for subtracting the second multiplication result from the first multiplication result to produce a real part Y.sub.0 of the complex result;
- and
- a third adder for adding the third multiplication result with the second multiplication result to produce an imaginary part y.sub.1 of the complex result;
- whereby the complex result is produced in one clock cycle.
Dependencies are inferred from the claim text.