Method apparatus and system for correlation

A data processing apparatus comprising:

• a plurality of data registers;
• an arithmetic logic unit having first and second data inputs connected to said plurality of data registers for multibit digital input signals, and a function control input for receiving a function signal, said arithmetic logic unit divided into a plurality of sections, each section generating a corresponding multibit digital resultant signal at an output representing a combination of respective subsets of said first and second inputs and said arithmetic logic unit having a status detector generating a single bit status signal corresponding to each multibit digital resultant signal;
• a muitiple flags register connected to said arithmetic logic unit for storing said single bit status signal for each section of said arithmetic logic unit;
• a multiplication unit having first and second inputs connected to said plurality of data registers for receiving multibit digital input signals, said multiplication unit generating a multibit digital product signal at an output representing the product of said third and fourth inputs;
• a source of a stream of instruction words;
• and
• an instruction decoder connected to said source of said stream of instruction words, said plurality of data registers, said arithmetic logic unit and flags register, said instruction decoder receiving individual instruction words of said stream of instruction words and responsive to a first instruction word to
• supply data from a first data register of said plurality of data registers to said first data input of said arithmetic logic unit,
• supply data from a second data register of said plurality of data registers to said second data input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to subtract data received at each section of said second data input from data received at corresponding sections of said first data input,
• store said multibit digital resultant signal of said arithmetic logic unit in a third data register of said plurality of data registers, and
• cause said status detector of said arithmetic logic unit to generate a single bit status signal indicating whether a corresponding section of said multibit digital resultant signal is less than zero;
• said instruction decoder responsive to a second instruction word to
• supply data corresponding to zero to said first data input of said arithmetic logic unit,
• supply data from said third data register to said second data input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to add data received at each section of said second data input to data received at said corresponding section of said first data input if said corresponding status signal has a first state and subtract data received at each section of said second data input from data received at said corresponding section of said first data input if said corresponding status signal has a second state, and
• store said multibit digital resultant signal of said arithmetic logic unit in a fourth data register;
• said instruction decoder responsive to a third instruction word to
• supply data stored in said fourth data register to both said first and second inputs of said multiplication unit,
• cause said multiplication unit to multiply said first input by said second input and produce a multibit digital product signal at said output,
• store said multibit digital product signal of said multiplication unit in a fifth data register;
• and
• said third instruction being repeated until each section of fourth data register has been multiplied by itself, said instruction decoder responsive to a fourth instruction word to
• supply data stored in said fifth data register to said first input of said arithmetic logic unit,
• supply data stored in a sixth data register to said second input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to add data received at each section of said second data input to data received said corresponding sections of at said first data input,
• store said multibit digital resultant signal of said arithmetic logic unit in a seventh data register of said plurality of data registers.

An data processing system comprising:

• an data system bus transferring data and addresses;
• a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus;
• an data processor circuit connected to said data system bus, said data processor circuit including
• a plurality of data registers;
• an arithmetic logic unit having first and second data inputs connected to said plurality of data registers for receiving multibit digital input signals representing corresponding first and second inputs, and a function control input for receiving a function signal, said arithmetic logic unit generating a multibit digital resultant signal at an output representing a combination of said first and second inputs corresponding to said function signal, said arithmetic logic unit having a status detector generating a single bit status signal indicating whether said multibit digital resultant signal is less than zero;
• a flag register connected to said arithmetic logic unit for storing said single bit status signal;
• a multiplication unit having first and second inputs connected to said plurality of data registers for receiving multibit digital input signals, said multiplication unit generating a multibit digital product signal at an output representing the product of said third and fourth inputs;
• a source of a stream of instruction words;
• and
• an instruction decoder connected to said source of said stream of instruction words, said plurality of data registers, said arithmetic logic unit, said flags register and said multiplication unit, said instruction decoder receiving individual instruction words of said stream of instruction words and responsive to a first instruction word to
• supply data from a first data register of said plurality of data registers to said first data input of said arithmetic logic unit,
• supply data from a second data register of said plurality of data registers to said second data input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to subtract data received at said second data input from data received at said first data input,
• store said multibit digital resultant signal of said arithmetic logic unit in a third data register of said plurality of data registers, and
• cause said status detector of said arithmetic logic unit to generate said single bit status signal indicating whether said multibit digital resultant signal is less than zero;
• said instruction decoder responsive to a second instruction word to
• supply data corresponding to zero to said first data input of said arithmetic logic unit,
• supply data from said third data register to said second data input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to add data received at said second data input to data received at said first data input if said single status bit has a first state and subtract data received at said second data input from data received at said first data input if said single status bit has a second state, and
• store said multibit digital resultant signal of said arithmetic logic unit in a fourth data register;
• said instruction decoder responsive to a third instruction word to
• supply data stored in said fourth data register to both said first and second inputs of said multiplication unit,
• cause said multiplication unit to multiply said first input by said second input and produce a multibit digital product signal at said output,
• store said multibit digital product signal of said multiplication unit in a fifth data register;
• and
• said instruction decoder responsive to a fourth instruction word to
• supply data stored in said fifth data register to said first input of said arithmetic logic unit,
• supply data stored in a sixth data register to said second input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to add data received at said second data input to data received at said first data input,
• store said multibit digital resultant signal of said arithmetic logic unit in a seventh data register of said plurality of data registers.

An data processing system comprising:

• an data system bus transferring data and addresses;
• a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus;
• an data processor circuit connected to said data system bus, said data processor circuit including
• a plurality of data registers;
• an arithmetic logic unit having first and second data inputs connected to said plurality of data registers for receiving multibit digital input signals, and a function control input for receiving a function signal, said arithmetic logic unit divided into a plurality of sections, each section generating a corresponding multibit digital resultant signal at an output representing a combination of respective subsets of said inputs and said arithmetic logic unit having a status detector generating a single bit status signal corresponding to each multibit digital resultant signal;
• a multiple flags register connected to said arithmetic logic unit for storing said single bit status signal for each section of said arithmetic logic unit;
• a multiplication unit having first and second inputs connected to said plurality of data registers for receiving multibit digital input signals, said multiplication unit generating a multibit digital product signal at an output representing the product of said third and fourth inputs;
• a source of a stream of instruction words;
• and
• an instruction decoder connected to said source of said stream of instruction words, said plurality of data registers, said arithmetic logic unit and flags register, said instruction decoder receiving individual instruction words of said stream of instruction words and responsive to a first instruction word to
• supply data from a first data register of said plurality of data registers to said first data input of said arithmetic logic unit,
• supply data from a second data register of said plurality of data registers to said second data input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to subtract data received at each section of said second data input from data received at corresponding sections of said first data input,
• store said multibit digital resultant signal of said arithmetic logic unit in a third data register of said plurality of data registers, and
• cause said status detector of said arithmetic logic unit to generate a single bit status signal indicating whether a corresponding section of said multibit digital resultant signal is less than zero;
• said instruction decoder responsive to a second instruction word to
• supply data corresponding to zero to said first data input of said arithmetic logic unit,
• supply data from said third data register to said second data input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to add data received at each section of said second data input to data received at said corresponding section of said first data input if said corresponding status signal has a first state and subtract data received at each section of said second data input from data received at said corresponding section of said first data input if said corresponding status signal has a second state, and
• store said multibit digital resultant signal of said arithmetic logic unit in a fourth data register;
• said instruction decoder responsive to a third instruction word to
• supply data stored in said fourth data register to both said first and second inputs of said multiplication unit,
• cause said multiplication unit to multiply said first input by said second input and produce a multibit digital product signal at said output,
• store said multibit digital product signal of said multiplication unit in a fifth data register;
• and
• said third instruction being repeated until each section of fourth data register has been multiplied by itself, said instruction decoder responsive to a fourth instruction word to
• supply data stored in said fifth data register to said first input of said arithmetic logic unit,
• supply data stored in a sixth data register to said second input of said arithmetic logic unit,
• supply a function signal to said function control input of said arithmetic logic unit to cause said arithmetic logic unit to add data received at each section of said second data input to data received said corresponding sections of at said first data input,
• store said multibit digital resultant signal of said arithmetic logic unit in a seventh data register of said plurality of data registers.