Asynchronous state machine attribute compeller

A digital circuit for compelling storage of an attribute and for providing output signals indicating status of said storage of said attribute, said digital circuit comprising:

• a digital storage device that can be set or cleared;
• a first combinational logic circuit connected to said digital storage device for setting said digital storage device to set said attribute based upon a group of first compelled inputs and a set-enable signal;
• a second combinational logic circuit connected to said digital storage device for clearing said digital storage device based upon a group of stable second compelled inputs and a clear-enable signal;
• a first logic gate connected to said digital storage device and said first combinational logic circuit for outputting a set-acknowledge signal which is representative of said attribute being set;
• and
• a second logic gate connected to said digital storage device and said second combinational logic circuit for outputting a clear-acknowledge signal which is representative of said digital storage device being cleared;
• wherein if said digital storage device is already set or is attempted to be set based on said group of first compelled inputs then said set-acknowledge signal goes to a logical high value regardless of said set-enable signal and once said set-acknowledge signal goes to a logical high value said attribute will not be reset in said digital storage device if such setting is subsequently attempted, and if said digital storage device is already cleared or is attempted to be cleared based on said group of second compelled inputs then said clear-acknowledge signal goes to a logical high value regardless of said clear-enable signal and once said clear-acknowledge signal goes to a logical high value said digital storage device will not be cleared in a subsequent attempt to do such.