High speed I.sub.DDQ monitor circuit

A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node, comprising the steps of:

• providing a reference current to the first node;
• decoupling a power supply from the first node;
• determining a first node voltage at a first time after the power supply is decoupled from the first node;
• determining the first node voltage at a second time after the first time;
• indicating that the I.sub.DDQ of the DUT is greater than the reference current if the first node voltage decreases from the first time to the second time;
• and
• indicating that the I.sub.DDQ of the DUT is less than the reference current if the first node voltage increases from the first time to the second time.

A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node, comprising the steps of:

• providing a reference current to the first node;
• decoupling a power supply from the first node;
• sampling a first node voltage at a first time after the power supply is decoupled from the first node;
• holding the first node voltage sampled at the first time as a reference voltage;
• comparing the first node voltage at a second time to the reference voltage;
• indicating that the I.sub.DDQ of the DUT is greater than the reference current if the first node voltage is less than the reference voltage;
• and
• indicating that the I.sub.DDQ of the DUT is less than the reference current if the first node voltage is greater than the reference voltage.