Reverse damascene via structures
AssigneeAdvanced Micro Devices, Inc.
InventorsYowjuang W. Liu, Kuang-Yeh Chang
Life of this patent
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Abstract
A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in dielectric layers, and filling them with barrier materials and plugs, is avoided along with their attendant disadvantages. The resulting semiconductor device exhibits improved reliability, higher operating speeds and an improved signal-to-noise ratio.
Claims22
A method of manufacturing a semiconductor device, which method comprises:
- depositing a plurality of sequential dielectric and conductive layers on a semiconductor substrate, each conductive layer comprising at least one conductive pattern;
- and
- forming an interconnection electrically connecting a conductive pattern of an upper conductive layer and a conductive pattern of a lower conductive layer by:
- depositing a first lower conductive layer;
- depositing a second conductive layer on and in electrical contact with the first conductive layer;
- etching the first lower conductive layer to form a conductive pattern comprising a conductive line;
- and
- etching the second conductive layer, after etching the first lower conductive layer, to form at least a portion of the interconnection from the remaining second conductive layer, wherein the width of the portion of the interconnection is less than the width of an underlying electrically connected etched conductive line.
A method of manufacturing a semiconductor device, which method comprises:
- depositing a first dielectric interlayer on a semiconductor substrate;
- depositing a first lower conductive layer on the first dielectric interlayer;
- depositing a second conductive layer on and in electrical contact with the first conductive layer;
- etching the first and second conductive layers to form at least one conductive pattern;
- forming a second dielectric interlayer;
- etching the second conductive layer, after forming the second dielectric interlayer, without substantially etching the first lower conductive layer to define at least a portion of an interconnection comprising remaining second conductive layer on and in electrical contact with a conductive pattern of the first lower conductive layer.
Dependencies are inferred from the claim text.