Direct memory access controller having programmable timing
AssigneeCompaq Computer Corporation
InventorsJeff W. Wolford, Robert Allan Lester
Life of this patent
Estimating the term…
Abstract
An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.
Claims10
A computer system, comprising:
- a microprocessor;
- a memory device;
- an I/O device;
- a bus on which write cycles and read cycles are run;
- said memory device and said I/O device being coupled to said bus;
- a controller for controlling data transfers between said memory device and said I/O device, each data transfer being performed in one data transfer cycle defined by an active period and an inactive period, said controller comprising:
- a first storage device for storing a value representing the active period, said active period value capable of being any one of a number of different values;
- a second storage device for storing a value representing the inactive period, said inactive period value capable &being any one of a number of different values;
- a data transfer circuit coupled to said bus and transferring data from said I/O device to the memory device in a data transfer cycle if a write cycle and from said memory device to said I/O device in a data transfer cycle if a read cycle, said transfer of data occurring during the active period of the data transfer cycle;
- and
- a timer coupled to said first and second storage devices and to said data transfer circuit for indicating when the end of the active period occurs and when the end of the inactive period occurs based on said active period and inactive period values stored in said first and second storage devices.
Dependencies are inferred from the claim text.