Digital signal processing system with dual memory structures for performing simplex operations in parallel

A digital signal processing system comprising:

• first and second register means for processing digital data,
• first memory means coupled to said first register means for storing a first plurality of data values, said first memory means being operative to transfer any of said first plurality of data values between said first memory means and said first register means,
• second memory means coupled to said second register means for storing a second plurality of data values, said second memory means being operative to transfer any of said second plurality of data values between said second memory means and said second register means,
• first and second multiplier means for producing first and second product outputs respectively, each of said first and second multiplier means being coupled to said first and second register means, wherein said second multiplier means is separate from said first multiplier means,
• arithmetic logic means having first, second and third inputs and an output, said first input being coupled to said first product output, said second and third inputs being selectively coupled to either of said second product output and said first and second register means, said arithmetic logic means output being coupled to said first and second register means for accumulating sample values in said first and second register means,
• instruction control means for storing a plurality of instruction op codes and controlling said system to compute said sample values by performing simplex operations during each cycle of a plurality of operating cycles of a first digital signal processing procedure;
• wherein said first plurality of data values in said first memory means are real data values and real coefficient values and said second plurality of data values in said second memory means are imaginary data values and imaginary coefficient values, and
• wherein said instruction op codes are programmable and operative to control said system to perform the following operations during a single operating cycle within said plurality thereof:
• (1) transferring a first data value within said plurality thereof from said first memory means to said first register means, (2) transferring a second data value within said plurality thereof from said second memory means to said second register means, (3) multiplying data on said first multiplier means and produce a first product output, (4) multiplying data on said second multiplier means and produce a second product output, (5) performing an arithmetic operation on said first, second, and third arithmetic logic output, and (6) transferring said arithmetic logic output to said first and second register means.