Bridge circuit for preventing data incoherency by holding off propagation of data transfer completion interrupts until data clears the bridge circuit

A bridge between a first bus and a second bus, comprising:

• a first bus master;
• a second bus master;
• a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising:
• a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty;
• and
• an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided when either said second bus interrupt signal is not received or said empty signal is not received.

A bridge between a first bus and a second bus, comprising:

• a first bus master;
• a second bus master;
• a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a plurality of second bus interrupt signals which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising:
• a plurality of data FIFOs for synchronizing data transfer between the first bus and the second bus, each data FIFO coupled between the first bus and the second bus, wherein each data FIFO provides an empty signal when said data FIFO is empty and wherein each data FIFO is associated with one of the plurality of second bus interrupt signals;
• and
• an interrupt control circuit receiving the plurality of second bus interrupt signals and said plurality of data FIFO empty signals and providing the first bus interrupt signal and said plurality of data FIFO empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when any of the second bus interrupt signal and the associated data FIFO empty signal are received, the first bus interrupt signal not provided when all of said second bus interrupt signals and said associated data FIFO empty signals are not received.

A disk array controller for coupling a disk array through an internal first bus of the controller to an external second bus comprising:

• a first bus internal to the controller;
• a first bus master;
• a bridge circuit for providing an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising:
• a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty;
• and
• an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided when either said second bus interrupt signal is not received or said empty signal is not received.

A computer system comprising:

• a disk drive array, comprising said disk array controller including:
• an internal first bus;
• a first bus master;
• a second bus internal to said disk array controller;
• said disk array controller further including:
• a bridge circuit for proving an interface between the first bus and the second bus, wherein the second bus provides a second bus interrupt signal which the bridge circuit provides to the first bus as a first bus interrupt signal, the bridge circuit comprising:
• a data FIFO for synchronizing data transfer between the first bus and the second bus, said data FIFO coupled between the first bus and the second bus, wherein said data FIFO provides an empty signal when said data FIFO is empty;
• and
• an interrupt control circuit receiving the second bus interrupt signal and said empty signal and providing the first bus interrupt signal to the first bus, the first bus interrupt signal provided when both said second bus interrupt signal and said empty signal are received, the first bus interrupt signal not provided with either said second bus interrupt signal is not received or said empty signal is not received.