US 5,692,170 AGranted

Apparatus for detecting and executing traps in a superscalar processor

AssigneeMetaflow Technologies, Inc.

InventorDavid L. Isaman

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Abstract

Apparatus for detecting and executing trapping program instructions in a superscalar processor operating on a plurality of pipelined instructions includes a fetch stage for fetching consecutive instructions from an instruction cache or from main memory, an instruction FIFO memory for storing fetched instructions from the fetch stage, and an instruction decode stage for removing instructions from the FIFO memory in accordance with relative ages of instructions stored in the FIFO memory. The decode stage examines instructions removed from the FIFO memory for trapping conditions, and flushes all younger instructions from the FIFO memory in response to identification of a trap in an instruction. The decode stage distinguishes between hardware traps and software traps. A software trapping instruction is forwarded to an execute stage for execution. The decode stage immediately causes the fetch address to be changed to the appropriate trap handler address.

Claims11

Dependent claims

A method of responding to trapping conditions in a pipelined superscalar computer, said computer comprising several processing stages including a decode stage for examining at each clock cycle one or more instructions from a sequence of instructions and a plurality of state registers coupled to the decode stage for indicating the operating state of the computer, and an execution stage coupled to said decode stage for receiving decoded instructions supplied by the decode stage, assessing whether any of said decoded instructions satisfies any of a first set of trapping conditions, and performing a specified trap action for any instruction that does satisfy any of said set,

said method comprising the steps at the decode stage of:
a) assessing whether any instruction being examined at the decode stage satisfies any of a second set of issue-time trapping conditions, said second set of issue-time traps being a subset of and disjointed from said first set of trapping conditions;
and
b) when any instruction so assessed at the decode stage is determined to satisfy one of said second set of issue-time trapping conditions, then performing at the decode stage the substeps of:
(i) preventing the first such instruction in said sequence, as well as all of the one or more instructions that follow said first such instruction in said sequence, from being supplied to the execution stage;
and
(ii) performing a specified trap action without waiting for completion of all previously issued instructions in the execution stage.

4 more elements

Dependencies are inferred from the claim text.