Prefetch buffer using flow control bit to identify changes of flow within the code stream

In a processor with a branch processing unit that detects changes of flow and supplies target addresses for prefetching prior to the associated change of flow (COF) instructions being decoded, a prefetch unit including a prefetch buffer with flow control for transferring instruction bytes to a decoder, comprising:

• (a) prefetch buffer means in the prefetch unit for storing prefetched instruction bytes for transfer to the decoder;
• (b) prefetch request means in the prefetch unit for selectively issuing prefetch requests for transferring a predetermined number of instruction bytes into the prefetch buffer means, including target prefetch requests using target addresses supplied by the branch processing unit prior to confirmation of the associated COF instruction;
• (c) the prefetch buffer means including a plurality of prefetch blocks of instruction bytes, each having associated with it a flow control indication of whether the prefetch block includes a predicted COF instruction;
• (d) flow control means for receiving the flow control indication for a current prefetch block when the transfer of instruction bytes from the current prefetch block is complete and the prefetch buffer increments to a next prefetch block for transferring instruction bytes to the decoder;
• (e) wherein, when the decoder has received all of the instruction bytes in the current prefetch block, if the flow control indication for that prefetch block indicates that it includes a predicted COF instruction, instruction bytes will not be transferred from the next prefetch block unless the predicted COF instruction is confirmed.

A method of controlling the flow of instruction bytes from a prefetch buffer to a decoder, used in a processor with a branch processing unit that detects changes of flow and supplies target addresses for prefetching prior to the associated change of flow (COF) instructions being decoded, comprising the steps:

• (a) storing in the prefetch buffer prefetched instruction bytes for transfer to the decoder;
• (b) selectively issuing prefetch requests for transferring a predetermined number of instruction bytes into the prefetch buffer, including target prefetch requests using target addresses supplied by the branch processing unit prior to confirmation of the associated COF instruction;
• (c) associating with each of a plurality of prefetch blocks of instruction bytes in the prefetch buffer, a flow control indication of whether the prefetch block includes a predicted COF instruction;
• (d) when the decoder has received all of the instruction bytes in a current prefetch block, if the flow control indication for that prefetch block indicates that it includes a predicted COF instruction, inhibiting transfer of instruction bytes from a next prefetch block unless the predicted COF instruction is confirmed.