Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor

A method for processing a stream of instructions in a pipelined computer including branch prediction and segmented memory, including the steps of:

• a) predicting a branch address to an undetermined memory segment;
• b) prefetching at least one predicted instruction at said branch address;
• c) predicting segment bits of said predicted instruction to be the same as the segment bits associated with the branch instruction immediately preceding the predicted instruction;
• d) decoding said predicted instruction using said predicted segment bits;
• e) during execution of said branch instruction, determining actual segment bits for said predicted code;
• and
• f) comparing said actual segment bits with said predicted segment bits, and performing the steps of
• if said actual segment bits are equivalent to said predicted segment bits, then continuing operation, and
• if said actual segment bits are not equivalent to said predicted segment bits, then flushing the pipeline and re-decoding and re-executing said predicted code using said actual segment bits.

A computer circuit for handling branch predictions in an instruction code that allows self-modifying code in a pipelined microprocessor having a prefetch stage for fetching and buffering instruction code lines from a computer memory, a decode stage coupled to the prefetch stage for receiving instruction code and decoding it into one or more instructions, and an execution stage, said microprocessor having a segmented memory, comprising:

• a branch prediction circuit for predicting a branch address responsive to a branch instruction;
• a segment prediction circuit for predicting segment bits for a predicted instruction;
• a branch instruction execution circuit in said execution stage for determining an actual target address and actual segment bits responsive to a branch instruction;
• segment register files holding actual segment bits received from said branch execution circuit;
• segment bit comparators for comparing predicted segment bits with the actual segment bits from the segment register file;
• a write address circuit, responsive to a write instruction in said execution stage, for supplying a write destination address;
• instruction pointer registers for holding current addresses of the instructions in prefetch stage, the decode stage, and the execution stage;
• write address comparators for comparing the addresses in said instruction pointer registers with said write destination address;
• and
• address control means, responsive to said address comparators and said segment bit comparators, for either continuing processing the instructions currently in said pipeline, or selecting an address to be prefetched.