Configurable digital signal interface using field programmable gate array to reformat data

A method for reformatting signals to be compatible with a computer system, comprising the steps of:

• receiving input signals having an input data type compatible with a source of the input signals, the source of the input signals external to the computer system,
• transporting first portions of the input signals along a first transport channel, the first portions having a first output data type compatible with the computer system,
• transporting second portions of the input signals along a second transport channel, the second portions of the input signals having a second output data type compatible with the computer system;
• wherein, each of the input signals is formed of a first signal portion combined with a second signal portion, and has a length different than a length of a signal compatible with the computer system.

An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising:

• a set of registers, each register in said set being configured to store a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length;
• a first buffer configured to receive first stored input signals having the second bit length in parallel from the set of registers and to store the received first stored input signals;
• a second buffer configured to receive second stored input signals having the second bit length in parallel from the set of registers and to store the received second stored input signals;
• and
• a controller configured to control the receipt of the first stored input signals by the first buffer and the second stored input signals by the second buffer, and to control transport of the received first stored input signals as output from the first buffer and the received second stored input signals as output from the second buffer to a memory of the computer system such that the transport of the received first stored input signals as output from the first buffer occurs simultaneous with receipt of the second stored input signals as input to the second buffer from the set of registers and the received first and the received second stored input signals are transported from the first and the second buffers as reformatted signals compatible with the computer system.

An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising:

• a first set of registers, each register within said first set being configured to store a first portion of a respective one of the input signals such that a total bit length of stored first portions in the first set of registers equals the second bit length;
• a second set of registers, each register within said second set being configured to store a second portion of a respective one of the input signals, such that a total bit length of stored second portions in the second set of registers equals the second bit length;
• a first buffer configured to receive the stored first portions in parallel from the first set of registers and to store the received first portions;
• a second buffer configured to receive the stored second portions in parallel from the second set of registers and to store the received second portions;
• and
• a controller configured to control transport of the first portions as output from the first buffer to a memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system , the transported first and second portions being reformatted signals compatible with the computer system.

A field programmable gate array for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising:

• a set of registers, each register being selectively configurable to store (i), in a first programmed configuration, a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length and (ii) in a second programmed configuration, only a portion of a respective one of the input signals such that a total bit length of stored portions in the set of registers equals the second bit length, and thereby reformat the input signals to be compatible with the computer system;
• a first buffer configurable to (i), in the first programmed configuration, receive first stored input signals having the second bit length in parallel from the set of registers and to store the first stored input signals and (ii), in the second programmed configuration, to receive the stored first portions in parallel from the set of registers and to store the received first portions;
• a second buffer configurable (i), in the first programmed configuration, to receive second stored input signals having the second bit length in parallel from the set of registers and to store the second stored input signals and (ii), in the second programmed configuration, to receive second portions of the input signals from a second set of registers and to store the received second portions;
• and
• a controller configurable to control (i), in the a first programmed configuration, transport of the first stored input signals as output from the first buffer to a memory of the computer system and to control simultaneous receipt of the second stored input signals as input to the second buffer from the set of registers and (ii), in the second programmed configuration, transport of the first portions as output from the first buffer to the memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system.