Circuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memory

In a computer system having a processor, a bus master, and a cache system, the cache system including a writeback cache memory controller connected to said processor and said bus master for monitoring operations of said processor and maintaining said cache system and for monitoring operations of said bus master and maintaining said cache system, cache data memory connected to said cache memory controller and coupled to said processor and to said bus master, cache tag memory connected to said cache memory controller for storing tag values associated with data stored in said cache system, cache valid memory connected to said cache memory controller for storing a valid status of data stored in said cache system, and cache dirty memory connected to said cache memory controller for storing a signal indicating a dirty status of data stored in said cache system, said cache memory controller improperly controlling said cache tag memory under predetermined certain conditions, including performance of non-cacheable operations when snoop or cache flush operations are not occurring, wherein said cache dirty memory includes an output for providing a dirty status signal, wherein said cache memory controller includes an input for receiving a cache dirty status signal, wherein said processor includes an output for providing a page cacheable status signal indicative of a cacheable status of a page and inputs for receiving signals for releasing address lines and for releasing address, data and control lines, a circuit for causing said cache memory controller to properly control said cache tag memories comprising:

• a first AND gate receiving at a first input said dirty status signal from said cache dirty memory and at a second input an indication developed from said page cacheable status signal that said page is not cacheable and providing an output signal;
• a second AND gate receiving at a first input said dirty status signal from said cache dirty memory and at a second input an indication that said releasing address, data and control lines signal is asserted and providing and output signal;
• a third AND gate receiving at a first input said dirty status signal from said cache dirty memory and at a second input an indication that said releasing address lines signal is asserted and providing an output signal;
• and
• an OR gate receiving the outputs of said AND gates at the inputs of said OR gate and having an output providing said cache dirty status signal to said cache memory controller
• wherein said circuit providing said cache dirty status signal under normal operations to said cache memory controller, said circuit masking said cache dirty status signal when a non-cacheable operation is occurring unless either a snoop operation or a cache flush operation is occurring so that said cache memory controller properly controls said cache tag memory.