US 5,692,153 A · Method and system for verifying execution order within a multiprocessor data processing system

Abstract

A method and system are disclosed for verifying consistency of an instruction execution order of a multiprocessor data processing system with a specified memory consistency model. Each processor within the multiprocessor data processing system executes instructions from an associated one of a number of instruction streams, which include instructions that store a number of unique values from multiple processors to a single selected address within memory. One of the unique values is loaded from the selected address to a particular processor within the data processing system. A set of valid values which may be returned by the loading step is determined according to the specified memory consistency model. By comparing the unique value with members of the set of valid values, the instruction execution order of the multiprocessor data processing system is verified. Utilizing the unique value which was returned by the load instruction, the set of valid values may then be updated.

Claims10

Dependent claims

A system for verifying consistency of an instruction execution order of a multiprocessor data processing system with a specified memory consistency model, said multiprocessor data processing system having plurality of processors and a memory, wherein each of said plurality of processors executes instructions from an associated instruction stream, said system comprising:

means for storing a plurality of unique values from said plurality of processors to a single selected location within said memory in an instruction execution order, said single selected location storing at most one of said plurality of unique values at a time;
means for loading a unique value among said plurality of unique values from said single selected location to a particular processor among said plurality of processors;
means for determining, in accordance with said specified memory consistency model, a set of valid values which may be loaded from said single selected location;
means for comparing said unique value with members of said set of valid values, and means for indicating that said instruction execution is improper in response to determining from said comparison that said unique value among said plurality of unique values is not a member of said set of valid values.

1 more element

A method, within a multiprocessor data processing system having a plurality of processors and a memory, for verifying consistency of an instruction execution order with a specified memory consistency model, wherein each of said plurality, of processors executes instructions from an associated instruction stream, said method comprising:

storing a plurality of unique values from said plurality of processors to a single selected location within said memory in an instruction execution order, said single selected location storing at most one of said plurality of unique values at a time;
loading a unique value among said plurality of unique values from said single selected location to a particular processor among said plurality of processors;
determining in accordance with said specified memory consistency model, a set of valid values which may be returned by said loading step;
comparing said unique value with members of said set of valid values, and in response to determining from said comparison that said unique value among said plurality of unique values is not a member of said set of valid values, indicating that said instruction execution order is improper.

1 more element

Dependencies are inferred from the claim text.

Method and system for verifying execution order within a multiprocessor data processing system

Life of this patent

Method and system for verifying execution order within a multiprocessor data processing system

Life of this patent

Abstract

Claims10