Master-slave cache system with de-coupled data and tag pipelines and loop-back

A master-slave cache system for access by a central processing unit's execution pipelines comprising:

• a slave cache for supplying instructions or operands to the CPU's execution pipelines;
• a master cache coupled to the slave cache and coupled to an external bus, the master cache organized as an N-way set-associative cache having N elements for each index-portion of an address, the master cache comprising:
• a tag RAM array for storing a tag and a master-valid indicator for each element for each index-portion of the address, the tag RAM array including slave-valid indicators for identifying elements in the tag RAM array which also have valid data in the slave cache, the master cache performing cache management operations for the slave cache by using the slave-valid indicators in the master cache;
• a data RAM array for storing sub-lines of data for each tag in the tag RAM array;
• a tag pipeline for accessing the tag RAM array, the tag pipeline having a plurality of stages for simultaneously processing a plurality of requests by passing the requests through successive stages of the tag pipeline in response to a clock;
• a data pipeline for accessing the data RAM array independently of the tag pipeline, the data pipeline having a plurality of stages simultaneously processing a plurality of requests by passing the requests through successive stages of the data pipeline in response to the clock;
• tag arbitration means, receiving a plurality of tag requests, for selecting a tag request from the plurality of tag requests for processing by the tag pipeline;
• data arbitration means, receiving a plurality of data requests, for selecting a data request from the plurality of data requests for processing by the data pipeline, the data arbitration means operating independently of the tag arbitration means;
• and
• source registers, coupled to the tag arbitration means and to the data arbitration means, for storing a plurality of requests for access of the master cache, including requests to access only the tag RAM array, requests to access only the data RAM array, and requests to access both arrays, the source registers storing completion status for each request;
• wherein the tag pipeline includes tag update means, coupled to the source registers, for updating the completion status for the request being processed by the tag pipeline;
• and wherein the data pipeline includes data update means, coupled to the source registers, for updating the completion status for the request being processed by the data pipeline,
• whereby the tag RAM array is accessed separately and independently from the data RAM array and whereby separate pipelines are used to access the tag RAM array and the data RAM array.