Method and apparatus for improving system memory cost/performance using extended data out (EDO)DRAM and split column addresses

An apparatus comprising:

• (a) a plurality of banks of extended data out dynamic random access memory (EDODRAM) for storing data;
• (b) address and control signal generation circuitry for receiving a start address of a memory access to the banks of EDODRAM, and in response, generating a series of memory addresses including a series of column addresses, and a plurality of control signals including a column address strobe (CAS) signal to perform the memory access,
• the column addresses being generated as a set of high order address bits common to all the column addresses, supplemented by particularized sets of low order address bits, one particularized set for each of the column addresses, and
• the CAS signal being generated with a plurality of corresponding active periods, one active period for each column address, with each active period being shorter in time than an amount of time required by a memory cell of the banks of EDODRAM to output or store data, to allow early precharge of memory cells of the banks of EDODRAM in preparation for response to the next column address;
• (c) a buffer coupled to the address and control signal generation circuitry for storing and outputting the set of high order address bits during the memory access to lower power required of the address and control signal generation circuitry to provide the set of high order address bits to the banks of EDODRAM;
• (d) a first address bus coupled to the buffer and the banks of EDODRAM for delivering the set of high order address bits to the banks of EDODRAM;
• and
• (e) a second address bus coupled to the address and control signal generation circuitry and the banks of EDODRAM for directly delivering the particularized sets of low order address bits to the banks of EDODRAM, bypassing the buffer, to allow the particularized sets of low order address bits, and therefore the column addresses, to be rapidly provided to the banks of EDODRAM.

In a computer system comprising system memory comprising a plurality of banks of extended data out dynamic random access memory (EDODRAM), a method for accessing the banks of EDODRAM, the method comprising the steps of:

• (a) receiving a start address of a memory access to the banks of EDODRAM;
• (b) generating a series of memory addresses including a series of column addresses, and a plurality of control signals including a column address strobe (CAS) signal to perform the memory access,
• the column addresses being generated as a set of high order address bits common to all the column addresses, supplemented by particularized sets of low order address bits, one particularized set for each of the column addresses, and
• the CAS signal being generated with a plurality of corresponding active periods, one active period for each column address, with each active period being shorter in time than an amount of time required by a memory cell of the banks of EDODRAM to output or store data, to allow early precharge of memory cells of the banks of EDODRAM in preparation for response to the next column address;
• (c) buffering and then outputting the set of high order address bits during the memory access to lower power required of the address and control signal generation circuitry to provide the set of high order address bits to the banks of EDODRAM;
• (d) delivering the set of high order address bits to the banks of EDODRAM via a first address bus coupling the buffer to the banks of EDODRAM;
• and
• (e) directly delivering the particularized sets of low order address bits to the banks of EDODRAM, via a second address bus coupling the address and control signal generation circuitry to the banks of EDODRAM, bypassing the buffer, to allow the particularized sets of low order address bits, and therefore the column addresses, to be rapidly provided to the banks of EDODRAM.