Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows by selectively transposing X and Y address portions, and programmable gate array applications thereof

A method of allocating memory to a programmable gate array having a plurality of programmable resources addressable per an x,y two-dimensional array, said method comprising steps of:

• providing a plurality of addressable memory units addressable by an N-bit address, said N-bit address having first, second and third portions;
• switchably associating the first and third portions of said N-bit address to respective x and y dimensions of the x,y two-dimensional array of the plurality of programmable resources in accordance with the second portion;
• and
• allocating memory units of the plurality of addressable memory units as addressed by said N-bit address to respective programmable resources of the plurality of programmable resources within the x,y two-dimensional array as addressed by the first and third portions of said N-bit address.

A computing system comprising:

• a plurality of programmable resources addressable per an x,y two-dimensional array;
• a plurality of addressable memory units addressable per an N-bit address;
• means for addressing the plurality of addressable memory units per a given N-bit address;
• means for using first, second and third portions of said N-bit address;
• and
• means for switchably addressing respective x and y addressable dimensions of the x,y two-dimensional array of the plurality of programmable resources with the first and third, or the third and first, portions respectfully of said given N-bit address in accordance with the second portion of said given N-bit address.

An improved computing system having:

• a field programmable gate array including a plurality of programmable resources addressable per respective x and y addresses of an x,y two-dimensional array;
• memory means including a plurality of memory units for storing configuration data of the field programmable gate array, the plurality of memory units being addressable per an N-bit address, the programmable resources of the plurality of programmable resources being associated with respective memory units of the plurality of memory units;
• and
• address means for addressing a programmable resource and a respective memory unit simultaneously for enabling transfer of configuration data from the memory unit to its associated programmable resource;
• wherein the improvement comprises means within the address means for dividing the N-bit address of the plurality of memory units into using first, second and third portions of the N-bit address, including means for using said first and third portions interchangeably, as a function of a value stored in said second portion, as the x and y, or y and x, addresses respectively for addressing the plurality of programmable resources.