VLIW processing device including improved memory for avoiding collisions without an excessive number of ports

A VLIW processing device comprising:

• an instruction register for holding a plurality of operations to be begun in a same operating cycle;
• a plurality of functional units for executing the plurality of operations in parallel;
• a plurality of memory units, each memory unit being permanently and directly connected to a single respective one of the functional units via a respective read port which supplies input data directly to the respective one of the functional units, at least one of the plurality of memory units having at least two write ports;
• and
• a unidirectional switching circuit for providing output signals from the plurality of functional units to write ports of the plurality of memory units, so that more than one of the plurality of functional units is enabled to write data simultaneously to a same one of the at least one of the plurality of memory units which has more than one write port, so that a collision in writing to that memory unit is avoided.

A processing device for executing operations comprising:

• a plurality of functional units for executing the operations in parallel;
• a plurality of memory units, each memory unit being permanently and directly connected to a single respective one of the functional units via a respective read port that supplies input data directly to the respective one of the functional units;
• a delay element permanently connected in parallel with the memory units;
• and
• a unidirectional switching circuit for providing output signals from the plurality of functional units to write ports of the plurality of memory units and to the delay element, so that
• at least one of the plurality of functional units is enabled to write data to one of the plurality of memory units that is connected with a target one of the functional units;
• and
• when two of the plurality of functional units need to write to the one memory unit that is connected to the target, output from one of the two is directed to the delay element instead, and thence via the switching circuit to the target, so that a collision is avoided.

A processing device for executing operations comprising:

• a plurality of functional units for executing the operations in parallel;
• a plurality of memory units, each memory unit being permanently and directly connected to a single respective one of the functional units via a respective read port that supplies input data directly to the respective one of the functional units, at least one of the plurality of memory units having at least two write ports;
• and
• a switching circuit for providing output signals from the plurality of functional units to write ports of the plurality of memory units, so that more than one of the plurality of functional units is enabled to write data simultaneously to a same one of the at least one of the plurality of memory units which has more than one write port, so that a collision in writing to that memory unit is avoided.