Flexible user interface circuit in a memory device
AssigneeIntel Corporation
InventorsMickey L. Fandrich, Richard J. Durante, Rodney R. Rozman
Life of this patent
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Abstract
A flash memory device having a flash cell array comprising a plurality of flash cells, a flash array controller circuit for performing program and erase operations on the flash cell array according to a queue operation, and an interface circuit for generating the queue operation according to a user command and a set of command parameters received over a host bus. The interface circuit determines a set of limited resource control bits for the user command and queues the user command and associated parameters to the flash array controller circuit.
Claims45
A flash memory device, comprising:
- interface circuit coupled to receive a user command and a set of command parameters over a bus, said command parameters comprising an address in a flash array of the flash memory device and data, the interface circuit having circuitry that allocates a set of limited resources in the flash memory device and that generates a set of limited resource control bits for the user command, said set of limited resources to process commands issued to the flash memory device;
- and
- controller circuit coupled to receive the user command, the command parameters and the limited resource control bits from the interface circuit and having circuitry that performs a program operation specified by the user command on a flash cell array and that also uses the limited resources specified by the limited resource control bits to perform the program operation.
A method for processing a user command in a flash memory device comprising a get of limited resources, said method comprising the steps of:
- receiving a user command and a set of command parameters over a bus, and determining a set of limited resource control bits for the user command, said command parameters comprising an address in a flash array of the flash memory device and data;
- buffering the user command, the command parameters and the limited resource control bits in an operation queue;
- and
- accessing the user command, the command parameters and the limited resource control bits from the operation queue and performing a program operation specified by the user command on a flash cell array using the set of limited resources specified by the limited resource control bits.
An apparatus for processing a user command in a flash memory device comprising a set of limited resources, said apparatus comprising:
- means for receiving a user command and a set of command parameters over a bus, and determining a set of limited resource control bits for the user command, said command parameters comprising an address in a flash array of the flash memory device and data;
- means for buffering the user command, the command parameters and the limited resource control bits in an operation queue;
- and
- means for accessing the user command, the command parameters and the limited resource control bits from the operation queue and performing a program operation specified by the user command on a flash cell array using the set of limited resources specified by the limited resource control bits.
A flash memory device, comprising:
- page buffer having a set of page planes for buffering data for transfer to a flash cell array during a program operation on the flash cell array;
- interface circuit coupled to receive a user command and a set of command parameters over a bus, said command parameters comprising an address in a flash array of the flash memory device and data, the interface circuit having circuitry for generating a set of limited resource control bits that specify one of the page planes for the user command;
- and
- controller circuit coupled to receive the user command, the command parameters and the limited resource control bits from the interface circuit and having circuitry that performs the program operation on the flash cell array using one of the page planes specified by the limited resource control bits.
A computer system, comprising:
- processor coupled to transfer a write data block over a bus and then a user command and a set of command parameters over the bus, said command parameters comprising an address in a flash array of a flash memory device and data;
- said flash memory device coupled to the bus and having an interface circuit that generates a set of limited resource control bits for the user command and that includes a page buffer having a set of page planes for buffering the write data block for transfer to a flash cell array during a program operation specified by the user command, the flash memory device also having a controller circuit coupled to receive the user command, the command parameters and the limited resource control bits from the interface circuit and having circuitry that performs the program operation on the flash cell array using one of the page planes specified by the limited resource control bits.
Dependencies are inferred from the claim text.