Master oriented bus bridge

An interface for transferring data between a master device on a first bus having timing controlled by a first clock and a slave device on a second bus having timing controlled by a second clock, the interface comprising:

• a buffer manager for producing a first control signal when a master write is attempted and a second control signal when a slave read is attempted;
• a first circuit, arranged to receive a clock signal from said first clock and said first control signal, for producing a write latch pulse signal based on said first clock signal;
• a second circuit, arranged to receive a clock signal from said second clock and said second control signal, for producing a read latch pulse signal based on said second clock signal;
• and
• a master buffer, arranged to receive write data from said first bus and read data from said second bus, and arranged to receive said write latch pulse signal and said read latch pulse signal, for producing as an output one of said write data latched by said write latch pulse signal and said read data latched by said read latch pulse signal in accordance with a control signal.