US 5,692,121 AGranted

Recovery unit for mirrored processors

AssigneeInternational Business Machines Corporation

InventorsFerenc Miklos Bozso, Yiu-Hing Chan, Philip George Emma, Algirdas Joseph Gruodis, David Patrick Hillerud, Scott Barnett Swaney

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Abstract

A method for making a processor system immune to circuit failure caused by external noise using mirrored processors, and a recovery unit integral with the method, are disclosed. Identical addresses and data information is generated in each of two processors. The data is then partitioned into registers and Error Correction Codes (ECC's) are generated for the data. The address, data, and ECC information for each processor is then interlaced in a data structure. The interlaced structures of each processor are then compared. If the comparison yields no errors, the data is checkpointed in the recovery unit; if an error is detected, a recovery sequence can be initiated after the check-stop operation, whereby the system is restored to the last error-free checkpointing operation.

Claims17

Dependent claims

A method for making a processor system immune to failure caused by external noise, said processor system having first and second identical processors running identical code in lock-step mode, including a recovery unit containing one or more checkpoint registers, each of said checkpoint registers having first and second partitions, the method comprising the steps of:

generating address data in each of said first and second processors;
generating identical operand data in each of said first and second processors;
initiating a fail-safe, no-fault error detection and recovery procedure comprising the steps of
partitioning the operand data generated by each of said first and second processors into respective first and second pluralities of data subsets,
generating error correction codes (ECCs) for each data subset of said first and second pluralities of data subsets,
bit interlacing the data subsets and corresponding ECCs to form an interlaced entity for each of said first and second processors, and
dividing each interlaced entity and loading the divide interlaced entities into first and second partitions of corresponding first and second current state registers;
and
concluding said fail-safe, no-fault error detection and recovery procedure by the further steps of
comparing corresponding portions of the divided interlaced entities of each of said first and second processors and said address data,
if all comparisons are equal, then checkpointing said first partition of an interlaced entity from said first processor stored in a first partition of said first set of current state registers into a corresponding first partition of a checkpoint register specified by said address data from said first processor, and checkpointing said second partition of the interlaced entity from the second processor stored in a second partition of said second set of current state registers into said second partition of the checkpoint register specified by said address data from said second processor, wherein said address data from said first and second processors is known to have been equal at the time of the comparison step, and
if not all comparisons are equal, then implementing a recovery sequence.

9 more elements

A recovery unit for a processor system including first and second identical processors running identical code in lock-step mode, comprising:

one or more of checkpoint registers, each of said checkpoint registers having first and second partitions;
means for separately storing identical operand data received from each of two processors;
means for initiating a fail-safe, no-fault error detection and recovery procedure, said creating means further comprising
means for partitioning the operand data received from each of said first and second processors into respective first and second pluralities of data subsets,
means for generating error correction codes (ECCs) for each data subset of said first and second pluralities of data subsets, and
means for bit interlacing the data subsets and corresponding ECCs to form an interlaced entity for each of said first and second processors, and
means for dividing each interlaced entity into first and second partitions and loading the divided interlaced entities into corresponding partitions of first and second sets of current state registers;
and
means for concluding said fail-safe, no-fault error detection and recovery procedure, said concluding means further comprising
means for comparing corresponding portions of the divided interlaced entities of each of said first and second processors,
means for checkpointing, if no errors are detected by said means for comparing, said first partition of an interlaced entity from said first processor stored in a first partition of said first set of current state registers into a corresponding first partition of a checkpoint register sniffed by address data from said first processor, and checkpoint said second partition of the interlaced entity from the second processor stored in a second partition of said second set of current state registers into said second partition of the checkpoint register specified by said address data from said second processor, wherein said address data from said first and second processors is known to have been equal at the time of the comparison is made by said means for comparing, and
means for recovery initiated by said means for comparing if errors are detected by said means for comparing.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/641,771Filed 30 Apr 1996 · continuation
Priority: 14 Apr 1995
Granted: 25 Nov 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 11/1641
Error detection by comparing the output of redundant processing systems: where the comparison is not performed by the redundant processing components
G06F 11/1008
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: in individual solid state devices
G06F
Computing and data processing