Phase locked loop including distributed phase correction pulses for reducing output ripple

Abstract

A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2. The controller controls the counter to count to a number P which is the largest power of 2 smaller than N, and prevents the counter from counting R=N-P pulses that are substantially evenly distributed within a period of the reference pulses such that the frequency of the VCO pulses is divided by N.

Dependencies are inferred from the claim text.