Bit synchronizer

A bit synchronizer for interpreting a bit data stream of preferably high data speed received by a receiver in a plesiochronous communication system, said synchronizer comprising:

• a first phase aligner and a second phase aligner for synchronizing;
• said first phase aligner being designated as a primary phase aligner and said second phase aligner being designated as a secondary phase aligner, said secondary phase aligner being deactivated into a standby state when the primary phase aligner delay is within a delay adjustment range,
• wherein when the primary phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between a system clock and said bit data stream, said second phase aligner is activated and becomes the primary phase aligner upon achieving a lock to said system clock, said first phase aligner then becomes the secondary phase aligner being deactivated into a standby state when the primary phase aligner is within its delay adjustment range, wherein the first phase aligner is ready to take over phase alignment when said second phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between said system clock and said bit data stream, wherein a function control alternates activation and deactivation of said respective first phase aligner and second phase aligner as primary and secondary phase aligners based on monitoring the operating point of a delay line delay control voltage of the primary phase aligner.

A bit synchronizer for interpreting a bit data stream of preferably high data speed received by a receiver in a plesiochronous communication system, said synchronizer comprising:

• a first phase aligner and a second phase aligner;
• said first phase aligner being designated as a primary phase aligner and said second phase aligner being designated as a secondary phase aligner, said secondary phase aligner being deactivated into a standby state when the primary phase aligner delay is within a delay adjustment range,
• wherein when the primary phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between a system clock and said bit data stream, said second phase aligner is activated and becomes the primary phase aligner upon achieving a lock to said system clock, said first phase aligner then becomes the secondary phase aligner being deactivated into a standby state when the primary phase aligner is within its delay adjustment range, wherein the first phase aligner is ready to take over phase alignment when said second phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between said system clock and said bit data stream, wherein a function control provides said first phase aligner with a phase adjustment range which extends from a minimum value to a first maximum value in the order of at least one unit interval, and provides said second phase aligner with a phase adjustment range which extends from the minimum value plus preferably at least one-half unit interval to a second maximum value;
• the total phase adjustment range corresponding to at least one unit interval.

A bit synchronizer for interpreting a bit data stream of preferably high data speed received by a receiver in a plesiochronous communication system, said synchronizer comprising:

• a first phase aligner and a second phase aligner;
• said first phase aligner being designated as a primary phase aligner and said second phase aligner being designated as a secondary phase aligner, said secondary phase aligner being deactivated into a standby state when the primary phase aligner delay is within a delay adjustment range,
• wherein when the primary phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between a system clock and said bit data stream, said second phase aligner is activated and becomes the primary phase aligner upon achieving a lock to said system clock, said first phase aligner then becomes the secondary phase aligner being deactivated into a standby state when the primary phase aligner is within its delay adjustment range, wherein the first phase aligner is ready to take over phase alignment when said second phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between said system clock and said bit data stream;
• and
• an adaptive reference generator which controls a function control for alternating activation and deactivation of said first and second phase aligners, wherein said adaptive reference generator uses third and fourth phase aligners which, in turn, are copies of the first and second phase aligners to be controlled;
• said third phase aligner operating at an absolute minimum delay level and said fourth phase aligner operating at a delay level which is controlled in a locked delay loop to be a predetermined number of half clock periods above the absolute minimum delay level.

A bit synchronizer for interpreting a bit data stream of preferably high data speed received by a receiver in a plesiochronous communication system, said synchronizer comprising:

• a first phase aligner and a second phase aligner, each having a delay adjustment range, said first phase aligner being designated as a primary phase aligner and said second phase aligner being designated as a secondary phase aligner, said secondary phase aligner being deactivated into a standby state when the primary phase aligner delay is within a delay adjustment range wherein when the primary phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between a system clock and said bit data stream said secondary phase aligner is activated and becomes the primary phase aligner upon achieving a lock with said system clock, and said first phase aligner then becomes the secondary phase aligner being deactivated in a standby state when the primary phase aligner is within its delay adjustment range, wherein said first phase aligner is ready to taking over phase alignment when said second phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between said system clock and said bit data stream and a changeover between the first and second phase aligners is effected continuously by shifting the working point between said first and second phase aligners by one-half local unit interval either up or down, and by alternating between the output from said first or second phase aligner and receiving data from both said first and second phase aligners during the alternating or switching period, said data differing by only one-half unit interval.

A bit synchronizer for interpreting a bit data stream of preferably high data speed received by a receiver in a plesiochronous communication system, said synchronizer comprising:

• a first phase aligner and a second phase aligner, each having a delay adjustment range, said first phase aligner being designated as a primary phase aligner and said second phase aligner being designated as a secondary phase aligner, said secondary phase aligner being deactivated into a standby state when the primary phase aligner delay is within a delay adjustment range wherein when the primary phase aligner is in danger of leaving its delay adjustment range as a result of following a varying phase relationship between a system clock and said bit data stream said secondary phase aligner is activated and becomes the primary phase aligner upon achieving a lock with said system clock;
• and an adaptive reference generator which controls a function control for alternating activation and deactivation of said first and second phase aligners, said adaptive reference generator uses third and fourth phase aligners which, in turn, are copies of the first and second phase aligners to be controlled, wherein a reference signal is generated by phase alignment of the output signal from said fourth phase aligner to the output signal from said third phase aligner, those being the subject of two digital signal patterns of which one signal pattern delivered to said third phase aligner is a delayed copy of the signal delivered to said fourth phase aligner, and this delay being a predetermined number of half clock periods where said predetermined number is a positive integer.