Encoding digital data
AssigneeSGS-Thomson Microelectronics S.A.
InventorChristopher Paul Hulme Walker
Life of this patent
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Abstract
An encoding scheme relies on a d.c. balanced code wherein each message to be transmitted is sent as a plurality of symbols, each symbol having six bits, three ones and three zeros. Out of the twenty combinations of balanced six-bit codes, two codes are reserved to operate as control tokens, being 010101 and 01010. Because of the particular format of the symbols, control tokens can be easily detected. Furthermore, they can be combined in longer bit sequences for use as initialisation and disconnect sequences.
Claims13
Data receiving circuitry including a synchronisation detection circuit comprising;
- a clock generator connected to receive an incoming stream of bits and to generate therefrom a bit clock having a clock edge defining each bit position in the bit stream;
- a counter arranged to receive the incoming bit stream and the bit clock and to count the number of successive transitions in the incoming bit stream and to provide a first output signal when the count is twelve;
- a clock divider for dividing the bit clock by twelve to produce a second output signal every twelfth clock edge;
- and
- a phase detector means for comparing said first and second output signals and for providing an error signal when they are out of phase.
A data receiving circuit comprising:
- a bit clock generator adapted to receive an incoming bit stream and to derive therefrom a bit clock;
- a first counter having a first input for receiving the incoming bit stream and a second input for receiving the bit clock, the first counter operable to generate a first output signal when the number of successive transitions in the incoming bit stream is at a first predetermined count;
- a clock divider that divides the bit clock by the first predetermined count to generate a second output signal;
- and
- a phase detector connected to the first counter and the clock divider and operable to generate an error signal when the first and second output signals are out of phase.
A method of detecting a synchronization error comprising the steps of:
- receiving an incoming bit stream;
- deriving a bit clock from the bit stream;
- generating a first output signal when the number of successive transitions in the bit stream is at a first predetermined count;
- generating a second output signal by dividing the bit clock by the first predetermined count;
- generating an error signal when the first and second output signals are out of phase;
- and
- generating a start signal when the number of successive transitions in the bit stream is at a second predetermined count, wherein the step of generating a first output signal includes the step of starting the count of the number of successive transitions in the bit stream upon generation of the start signal.
Dependencies are inferred from the claim text.