Data transmission protection circuit with error correction

A protection system for transmitting selected data bits to a receiving station, said system interconnectable to at least first and second data transmission lines, each of said lines carrying a series of data bits substantially following a predetermined coding rule, said system comprising, in combination:

• a controller;
• first and second bi-polar to bit stream converters, interconnected, respectively, to said first and second transmission lines;
• first and second pairs of build-out circuits, interconnected, respectively, to said first and second bi-polar to bit stream converters, for receiving and storing build-out sequences of data bits from said transmission lines and advising said controller of said build-out sequences, said controller correlating bits from said first pair of build-out circuits with bits from said second pair of build-out circuits, said controller further detecting when one particular pair of correlated bits follows said coding rule and a second pair of correlated bits violates said coding rule;
• first and second pairs of buffer shift registers for receiving and storing buffer sequences of data bits from, respectively, said first and second pairs of build-out circuits, and a particular one of said first and second pairs of buffer shift registers carrying said particular correlated bits that follow said coding rule;
• and
• a switch, interconnected to said buffer shift registers and responsive to said controller, for transmitting data bits to said receiving station from said particular pair of buffer shift registers carrying said particular correlated bits that follow said coding rule.

A data protection system for providing uninterrupted data transmission to a receiving station by sending a data bit stream following a predetermined coding rule on each of a plurality of data transmission lines, said system comprising in combination:

• a plurality of shift registers, each shift register operatively connected to a respective transmission line for receiving and storing a block of bits transmitted on said respective transmission line and having a series of taps with each tap providing a respective bit in said block of bits;
• a correlator, operatively connected to said plurality of shift registers, for determining a respective transmission delay lag for each transmission line by comparing locations of correlated bits within each of said plurality of shift registers;
• and
• a delay interface, operatively connected to said correlator and said plurality of transmission lines, for providing a respective delay after each of said plurality of transmission lines by tapping off from a respective correlated tap on said series of taps of said respective shift register for each of said transmission lines, wherein said respective correlated tap is determined from said respective delay lag such that correlated bits from each of said transmission lines leave from said shift registers at substantially same times.

A data protection system for reducing a bit error rate in transmission of a data bit stream following a predetermined coding rule to a receiving station, wherein said data bit stream is transmitted on each of a plurality of data transmission lines, said system comprising in combination:

• a plurality of build-out circuits, each build-out circuit operatively connected to a respective transmission line and including a respective shift register for receiving and storing a block of bits transmitted on said respective transmission line and having a series of taps with each tap providing a respective bit in said block of bits;
• a correlator, operatively connected to said shift registers, for determining a respective delay lag for each transmission line by comparing locations of correlated bits within each of said plurality of shift registers;
• a delay interface, operatively connected to said correlator and said plurality of transmission lines, for providing a respective delay after each of said plurality of transmission lines by tapping off from a respective correlated tap on said series of taps of said respective shift register for each of said transmission lines, wherein said respective correlated tap is determined from said respective delay lag such that said correlated bits from each of said transmission lines leave from said shift registers at substantially same times;
• a controller, operatively connected to each of said correlated taps, and including a computational module for continuously determining which of said transmission lines has transmitted a respective sequence of data bits violating said predetermined coding rule, said respective sequence of data bits for each transmission line being received by said controller from said respective correlated tap, and wherein said controller includes:
• a transmission line selector for continuously selecting a selected transmission line, as one of said plurality of transmission lines, having a respective sequence of data bits that substantially follows said predetermined coding rule;
• and
• a switch, operatively connected to said correlated taps and said transmission line selector, for allowing through only data from a respective correlated tap of said selected transmission line to said receiving station.

A method for controlling bit error rates in a data transmission system, the method including the steps of:

• A. sending a respective sequence of data bits on each of a plurality of transmission lines, each respective sequence of data bits being coded to follow a predetermined coding rule;
• B. storing blocks of bits from said respective sequence of data bits in a respective build-out circuit having a respective shift register for each data transmission line after a predetermined distance of transmission on said transmission lines, said respective shift register having a series of taps with each tap providing a respective bit in said blocks of bits;
• C. determining a respective delay lag for each transmission line by comparing locations of correlated bits within each of said plurality of shift registers;
• D. providing a respective delay after each of said plurality of transmission lines by tapping off from a respective correlated tap on said series of taps of said respective shift register for each of said transmission lines, wherein said respective correlated tap is determined from said respective delay lag such that correlated bits from each of said transmission lines leave from said shift registers at substantially same times;
• E. determining continuously which of said transmission lines has transmitted a respective sequence of data bits violating said predetermined coding rule, said respective sequence of data bits for each transmission line being received by said controller from said respective correlated tap;
• F. selecting continuously a selected transmission line, as one of said plurality of transmission lines, having a respective sequence of data bits that substantially follows said predetermined coding rule;
• and
• G. switching through only data from a respective correlated tap of said selected transmission line to said receiving station.

A method for providing uninterrupted data transmission to a receiving station, said method comprising, in combination:

• sending a data bit stream according to a predetermined coding rule along a first transmission line and along a second transmission line, said first transmission line being operatively interconnected to a first shift register for holding bits of data transmitted along said first transmission line, and said second transmission line being operatively interconnected to a second shift register for holding bits of data transmitted along said second transmission line,
• storing a first block of bits transmitted along said first transmission line in said first shift register and staring a second block of bits transmitted along said second transmission line in said second shift register, said first shift register having a series of first taps, each of said first taps providing a respective bit in said first block of bits, and said second shift register having a series of second taps, each of said second taps providing a respective bit in said second block of bits;
• determining a delay lag between said first transmission line and said second transmission line by correlating bits in said first and second shift registers and comparing locations of correlated bits between said first shift register and said second shift register;
• and
• aligning said bit streams along said first and second transmission lines by tapping off at least one of said bit streams from a tap, said tap being selected based on said delay lag.