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US 5,691,996 AGranted
Memory implemented error detection and correction code with address parity bits
AssigneeInternational Business Machines Corporation
InventorsChin-Long Chen, Mu-Yue Hsiao, Walter Heinrich Lipponer, William Wu Shen
Life of this patent
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Abstract
A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received.
Claims2
A method of generating at least two address parity bits in a computer system from a string of received incoming system address bits, said incoming address bits comprising a vector with a multiplicity of lines each having segments b bits in length, said method comprising the steps of:
- dividing said vector lines into two groups as to provide at least two bits of address parity, wherein said first group having only high bits with a value of "1", and said second group having only low bits with a value of "0";
- generating at least one address parity bit from each of said two groups by combining all bits of said first group to generate at least one high address parity bit, and combining all bits of said second group to generate at least one low address parity bit;
- said vector and said address parity having the following values:
- ______________________________________ =======================DATA======================= 1 2 3 4 5 6 7 8 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1000 1000 1000 1000 1000 1000 1000 1000 0100 0100 0100 0100 0100 0100 0100 0100 0010 0010 0010 0010 0010 0010 0010 0010 0001 0001 0001 0001 0001 0001 0001 0001 0110 1000 0010 1011 1010 1101 0101 1110 1101 0100 0001 0110 0101 1011 1111 1001 1011 0010 1010 1101 1000 0110 0100 1001 0110 0001 0101 1011 0100 1101 1100 0111 1000 1110 0111 1010 1001 0010 0110 0001 0100 1001 1110 0101 0111 0001 1101 0011 0010 1001 1110 1000 0111 1010 1011 0101 0001 0111 1001 0100 1110 0101 0110 1111 ====================================================== ______________________________________ =======================DATA======================= 9 10 11 12 13 14 15 16 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1001 1101 1111 0011 1100 1100 1110 0110 0111 1011 1010 0010 1000 1000 1001 1101 0111 0110 1100 1111 0011 0011 1001 1011 1110 1101 1000 1010 0010 0010 0111 0110 1000 0001 1000 0111 1000 1110 1000 0100 0100 0011 0100 1110 0100 1001 0100 1100 0010 0101 0010 1110 0010 1001 0010 0001 0001 1111 0001 1001 0001 0111 0001 0011 0101 1000 1011 1000 0110 1000 0100 1000 1111 0100 0110 0100 1101 0100 1100 0100 0100 0010 1101 0010 1011 0010 0001 0010 1100 0001 1011 0001 0110 0001 0011 0001 ====================================================== ______________________________________ ==== ECC ==== ======= ADDRESS SYMBOL PARITY ID BITS 17 18 19 (CHIP) 20 ==== ==== ==== ID ==== ______________________________________ 1000 0000 0000 -- 01 0100 0000 0000 -- 11 0010 0000 0000 -- 10 0001 0000 0000 -- 11 0000 1000 0000 -- 10 0000 0100 0000 -- 01 0000 0010 0000 -- 00 0000 0001 0000 -- 00 0000 0000 1000 -- 00 0000 0000 0100 -- 00 0000 0000 0010 -- 01 0000 0000 0001 -- 10 ====================================================== ______________________________________
1 more element
A method of generating at least two address parity bits in a computer system from a string of received incoming system address bits, said incoming address bits comprising a vector with a multiplicity of lines each having segments b bits in length, said method comprising the steps of:
- dividing said vector lines into eight groups so as to provide at least two bits of address parity, wherein said first group having only high bits with a value of "1", and said second group having only low bits with a value of "0";
- generating at least one address parity bit from each of said two groups by combining all bits of said first group to generate at least one high address parity bit, and combining all bits of said second group to generate at least one low address parity bit;
- said vector and said address parity comprising:
- ______________________________________ =======================DATA======================= 1 2 3 4 5 6 7 8 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1000 1000 1000 1000 1000 1000 1000 1000 0100 0100 0100 0100 0100 0100 0100 0100 0010 0010 0010 0010 0010 0010 0010 0010 0001 0001 0001 0001 0001 0001 0001 0001 0110 1000 0010 1011 1010 1101 0101 1110 1101 0100 0001 0110 0101 1011 1111 1001 1011 0010 1010 1101 1000 0110 0100 1001 0110 0001 0101 1011 0100 1101 1100 0111 1000 1110 0111 1010 1001 0010 0110 0001 0100 1001 1110 0101 0111 0001 1101 0011 0010 1001 1110 1000 0111 1010 1011 0101 0001 0111 1001 0100 1110 0101 0110 1111 ====================================================== ______________________________________ =======================DATA======================= 9 10 11 12 13 14 15 16 ==== ==== ==== ==== ==== ==== ==== ==== ______________________________________ 1001 1101 1111 0011 1100 1100 1110 0110 0111 1011 1010 0010 1000 1000 1001 1101 0111 0110 1100 1111 0011 0011 1001 1011 1110 1101 1000 1010 0010 0010 0111 0110 1000 0001 1000 0111 1000 1110 1000 0100 0100 0011 0100 1110 0100 1001 0100 1100 0010 0101 0010 1110 0010 1001 0010 0001 0001 1111 0001 1001 0001 0111 0001 0011 0101 1000 1011 1000 0110 1000 0100 1000 1111 0100 0110 0100 1101 0100 1100 0100 0100 0010 1101 0010 1011 0010 0001 0010 1100 0001 1011 0001 0110 0001 0011 0001 ====================================================== ______________________________________ ==== ECC ==== ======= ADDRESS SYMBOL PARITY ID BITS 17 18 19 (CHIP) 20 21 ==== ==== ==== ID ==== ==== ______________________________________ 1000 0000 0000 -- 0111 1101 0100 0000 0000 -- 1111 0010 0010 0000 0000 -- 1011 0111 0001 0000 0000 -- 1100 1101 0000 1000 0000 -- 1000 0011 0000 0100 0000 -- 0110 0111 0000 0010 0000 -- 0001 0010 0000 0001 0000 -- 0000 1110 0000 0000 1000 -- 0000 1100 0000 0000 0100 -- 0001 1010 0000 0000 0010 -- 0110 1000 0000 0000 0001 -- 1011 1001 ====================================================== ______________________________________
1 more element
Dependencies are inferred from the claim text.