Hybrid partial scan method

A method for testing a digital integrated circuit having a plurality of flip-flops comprising the steps of:

• a) partitioning the faults in the circuit into a first fault type and a second fault type;
• b) selecting a static characterization algorithm for characterizing the first and second fault types, the selecting step comprising the steps of:
• providing a set of static characterization algorithms,
• calculating a characteristic Ce for all the faults of the first type, as a class, according to each algorithm provided in the providing step,
• calculating a characteristic Ch for all the faults of the second type, as a class, according to each algorithm provided in the providing step, and
• determining which algorithm yields the maximum ratio of Max(Ce,Ch)/Min(Ce,Ch),
• c) determining the relationship between attainable fault coverage and the characterized values for the first and second fault types;
• d) characterizing the first and second fault types for each candidate flip-flop for scan in the digital integrated circuit with the selected static characterization algorithm;
• e) determining the first and second fault types that are the closest together in value;
• f) selecting the flip-flop associated with the first and second fault types determined in step (e);
• g) forming a shift register with the flip-flop selected in step (f);
• h) repeating steps (d)-(g) until the attainable fault coverage determined in step (c) is attained;
• and
• i) generating test data for a network with the shift register configured in step (h).

A method for testing a digital integrated circuit having N flip-flops comprising the steps of:

• a) partitioning the faults in the circuit into a first fault type and a second fault type;
• b) selecting a static characterization algorithm for characterizing the first and second fault types, the selecting step comprising the steps of:
• providing a set of static characterization algorithms,
• calculating a characteristic Ce for all the faults of the first type, as a class, according to each algorithm provided in the providing step,
• calculating a characteristic Ch for all the faults of the second type, as a class, according to each algorithm provided in the providing step, and
• determining which algorithm yields the maximum ratio of Max(Ce,Ch)/Min(Ce,Ch),
• c) determining the relationship between attainable fault coverage and the characterized values for the first and second fault types;
• d) characterizing the first and second fault types for each candidate flip-flop for scan by calculating characteristics Ce and Ch' for each candidate flip-flop with the selected static characteristic algorithm wherein Ch' is a new value of Ch;
• e) determining the first and second fault types that are the closest together in value by determining which new value Ch' is closest to Ce;
• f) selecting the flip-flop associated with the value Ch' determined in step (e);
• g) forming a shift register with the flip-flop selected in step (f);
• h) repeating steps (d)-(g) until the attainable fault coverage determined in step (c) is attained;
• and
• i) generating test data for a network having the shift register configured in step (h).