Address buffer for high speed static random-access-memory devices

Abstract

An address buffer for high speed static random-access-memory (SRAM) devices is disclosed. The address buffer includes a buffer stage, an out-phase variable buffer circuit and an in-phase variable buffer circuit. The buffer stage includes a number of series-connected buffer units for transmitting an input address signal. The out-phase variable buffer circuit is connected to the buffer stage for providing a first buffer condition in a write period and for providing a second buffer condition in a read period. The in-phase variable buffer circuit is also connected to the buffer stage for providing a third buffer condition in the write period and for providing a fourth buffer condition in the read period. An external address signal can be delayed by the various buffer conditions of the address buffer during the write period to optimize the operation of the SRAM devices, and the various buffer conditions will not affect the read period.

Dependencies are inferred from the claim text.