Semiconductor memory device and memory module using the same
AssigneesHitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.
InventorsToshio Sasaki, Kazumasa Yanagisawa, Toshio Sugano, Kiyoshi Inoue, Seiichiro Tsukui, Masakazu Aoki, Shigeru Suzuki, Masashi Horiguchi
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Abstract
Input/output terminals of a first semiconductor memory device in which failures or defects exist in units of memory mats and input/output terminals of a second semiconductor memory device having redundant memory mats are connected to one another on a mounted substrate to thereby relieve the failures in the memory mat units. A power source is substantially cut off from supplying to a faulty memory mat.
Claims5
A semiconductor memory device comprising:
- a first input buffer for receiving an address signal therein;
- an address selection circuit for selecting a memory cell based on the address signal input through said first input buffer;
- a second input buffer for receiving therein a signal to be written into the memory cell;
- an output buffer for outputting a signal read from the memory cell;
- a sense amplifier connected to the memory cell so as to obtain the read signal;
- a storing circuit for storing malfunction information;
- and
- a power cut-off circuit for interrupting an operating voltage to said sense amplifier in response to the malfunction signal stored in said storing means;
- wherein outputs produced from said first and second input buffers and said output buffer are brought into high impedance based on the malfunction information.
A memory module having a plurality of semiconductor memory devices, comprising:
- a plurality of memory mats included in first semiconductor memory devices of said plurality of semiconductor memory devices respectively, said each memory mat comprising:
- a first input buffer for receiving an address signal therein;
- an address selection circuit for selecting a memory cell based on the address signal input through said first input buffer;
- a second input buffer for receiving therein a signal to be written into the memory cell;
- an output buffer for outputting a signal read from the memory cell;
- a sense amplifier connected to the memory cell so as to obtain the read signal;
- a storing circuit for malfunction information;
- and
- a power cut-off circuit for interrupting an operating voltage to said sense amplifier in response to the malfunction signal stored in said storing means;
- wherein outputs produced from said first and second input buffers and said output buffer are brought into high impedance based on the malfunction formation;
- and
- second semiconductor memory devices of said plurality of semiconductor memory devices including redundant memory mats for respectively relieving defective memory mats in said first semiconductor memory devices.
Dependencies are inferred from the claim text.