Staggered row line firing in single ras cycle
AssigneeMicron Technology, Inc.
InventorJames P. Rupp
Life of this patent
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Abstract
A row decoder circuit operates in a memory integrated circuit, such as a dynamic random access memory (DRAM), having an array of memory cells including row and columns. An address decode tree circuit receives address signals and provides decode signals being activated based on the state of the address signals. Row line driver circuits receive corresponding ones of the decode signals and an enable signal. Each row line driver circuit fires a corresponding row line when the enable signal is activated and the corresponding one of the decode signals is activated. Delay circuitry delays certain of the address signals to stagger the activation of certain of the decode signals to permit multiple row lines to fire in a single row address strobe (RAS) cycle.
Claims22
A row decoder circuit in a memory integrated circuit having an array of memory cells including row and columns, the row decoder comprising:
- an address decode tree circuit receiving address signals and providing N decode signals being activated based on the state of the address signals;
- N row line driver circuits, each receiving a corresponding one of the N decode signals and an enable signal, and each row line driver circuit firing a corresponding row line when the enable signal is activated and the corresponding one of the N decode signals is activated;
- and
- delay circuitry coupled to the address signals to delay certain of the address signals to stagger the activation of certain of the decode signals.
A memory integrated circuit comprising:
- a memory array having rows and columns, wherein a given row is addressed for reading or writing by firing a row line;
- an address decode tree circuit receiving address signals and providing N decode signals being activated based on the state of the address signals;
- N row line driver circuits, each receiving a corresponding one of the N decode signals and an enable signal, and each row line driver circuit firing a corresponding row line when the enable signal is activated and the corresponding one of the N decode signals is activated;
- and
- delay circuitry coupled to the address signals to delay certain of the address signals to stagger the activation of certain of the N decode signals.
A method of firing multiple row lines in a single row address strobe (RAS) cycle in a memory integrated circuit having an array of memory cells including row and columns, the method comprising the steps of:
- activating an enable signal at least by a first time, wherein the enable signal being activated causes a selected row line driver to fire a corresponding row line;
- activating at least a first address signal at least by the first time, wherein the at least first address signal being activated selects at least a first row line driver to be fired;
- activating at least a second address signal at a second time, which occurs after the first time wherein the at least second address signal being activated selects at least a second row line driver to be fired;
- and
- activating at least a third address signal at a third time which occurs after the second time, wherein the at least third address signal being activated selects at least a third row line driver to be fired, wherein the first, second, and third times all occur in a single RAS cycle.
A method of firing N row lines in a single row address strobe (RAS) cycle in a memory integrated circuit having an array of memory cells including row and columns, the method comprising the steps of:
- activating an enable signal at least by a first time, wherein the enable signal being activated causes a selected row line driver to fire a corresponding row line;
- activating address signals corresponding to the N rows;
- decoding the activated address signals to provide N decode signals being activated based on the state of the address signals;
- firing a corresponding row line when the enable signal is activated and the corresponding one of the N decode signals is activated;
- and
- delaying certain of the address signals to stagger the activation of certain of the decode signals.
Dependencies are inferred from the claim text.