Device and method for isolating bit lines from a data line

A memory device, comprising:

• a memory-block select circuit;
• a column select circuit;
• a global data line;
• and
• a plurality of memory blocks each coupled to said global data line, each memory block comprising,
• a plurality of column lines,
• a local data line, and
• a plurality of memory cells arranged in columns and each coupled to a corresponding one of said column lines,
• each memory block having associated therewith,
• a switch circuit having a control terminal coupled to said memory-block select circuit, a first switch terminal coupled to said global data line, and a second switch terminal coupled to said local data line,
• an isolation-signal generator having an input terminal coupled to said memory-block select circuit and having an output terminal,
• a plurality of switches each having a control terminal, a first switch terminal coupled to a corresponding one of said column lines, and a second switch terminal coupled to said local data line, and
• a plurality of control circuits each having a first input terminal coupled to said column select circuit, a second input terminal coupled to said output terminal of said isolation-signal generator, and an output terminal coupled to said control terminal of a corresponding one of said switches.

A computer system, comprising:

• a data input device;
• a data output device;
• an address bus;
• a system data bus having one or more system data lines;
• and
• computing circuitry coupled to said data input device, said data output device, said address bus, and said data bus, said computing circuitry including a memory device that includes,
• an address decoder coupled to said address bus,
• a global data line that is coupled to one of said system data lines, and
• a plurality of memory blocks each coupled to said global data line, each memory block comprising,
• a plurality of column lines,
• a local data line,
• a switch circuit having a control terminal coupled to said address decoder, a first switch terminal coupled to said global data line, and a second switch terminal coupled to said local data line,
• a plurality of memory cells arranged in columns and each coupled to a corresponding one of said column lines,
• an isolation-signal generator having an input terminal coupled to said address decoder and having an output terminal,
• a plurality of switches each having a control terminal, a first switch terminal coupled to a corresponding one of said column lines, and a second switch terminal coupled to said local data line, and
• a plurality of control circuits each having a first input terminal coupled to said address decoder, a second input terminal coupled to said output terminal of said isolation-signal generator, and an output terminal coupled to said control terminal of a corresponding one of said switches.

A memory device, comprising:

• an address decoder;
• a global data line;
• and
• a plurality of memory blocks each coupled to said address decoder and said global data line, each memory block comprising,
• a plurality of column lines,
• a local data line,
• a plurality of memory cells arranged in columns and each coupled to a corresponding one of said column lines,
• a column-select circuit coupled to said column lines and to said local data line, said column-select circuit operable to couple a selected column line to said local data line when said memory block is selected, and to uncouple each of said column lines from said local data line a predetermined time period after a read cycle begins with respect to said selected memory block, and
• said column-select circuit operable to uncouple each of said column lines from said local data line when said memory block is unselected.