Technique for reconfiguring a high density memory

An integrated circuit memory, comprising:

• an array of memory cells including a plurality of sectors;
• a decoder, responsive to memory addresses within an address space, to access memory cells in the plurality of sectors;
• and
• programmable circuitry to configure the decoder so that the address space is reduced and a subset including one or more of the plurality of sectors is disabled and remaining sectors are accessed by sequential addresses.

An integrated circuit memory, comprising:

• an array of floating gate memory cells including a plurality of sectors, wherein the plurality of sectors are identified by an N bit field in a memory address having an m bit subfield and an N-m bit subfield;
• read, program and erase resources which program using a process which involves applying a negative voltage to a wordline of a cell to be programmed;
• a decoder, responsive to memory addresses, to access memory cells in the plurality of sectors;
• programmable circuitry to configure the decoder so that one or more of the plurality of sectors is disabled and remaining sectors are accessed by sequential addresses, including logic which divides the array into a first subset including sectors having a particular m bit subfield of the N bit field at a first value, and a second subset including sectors having the particular m bit subfield of the N bit field different than the first value, and substitutes in the sequential addressing a defective sector in the first subset with a substitute sector in the second subset;
• and
• logic which prevents the negative voltage from being applied to wordlines in disabled sectors.

A method for configuring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address, comprising:

• detecting defective sectors in the array;
• and
• partitioning the array to disable defective sectors by configuring the address decoder to prevent access to the defective sectors while maintaining sequential addressing of remaining sectors in the array;
• and
• wherein the step of partitioning includes configuring the address decoder to replace a defective sector in the array by another sector in the array having N-m of the N address bits address bits in common with the defective sector, where m is between 1 and N-1.

A method for configuring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address, comprising:

• detecting defective sectors in the array;
• and
• partitioning the array to disable defective sectors by configuring the address decoder to prevent access to the defective sectors while maintaining sequential addressing of remaining sectors in the array;
• and
• wherein the step of partitioning includes configuring the address decoder to enable a first subset and disable a second subset of the plurality of sectors having p of the N address bits in common, and to replace a defective sector in the first subset by another sector in the second subset having at least one of the other N-p address bits in common with the defective sector, where p is between 1 and N-1.

A method for configuring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address, comprising:

• detecting defective sectors in the array;
• partitioning the array to disable defective sectors by configuring the address decoder to prevent access to the defective sectors while maintaining sequential addressing of remaining sectors in the array;
• and
• wherein the memory array comprises floating gate memory cells which are programmed by a process involving applying a negative voltage to wordlines connected to the cells, and the step of partitioning includes preventing wordlines in disabled sectors from receiving the negative voltage.

An integrated circuit memory, comprising:

• an array of memory cells including a plurality of sectors;
• a decoder, responsive to memory addresses, to access memory cells in the plurality of sectors;
• and
• programmable circuitry to configure the decoder so that a subset including one or more of the plurality of sectors is disabled and remaining sectors are accessed by sequential addresses;
• and
• wherein the plurality of sectors are identified by an N bit field in a memory address, and the disabled subset includes sectors having m of the N bits in common, where m is between 1 and N-1.

An integrated circuit memory, comprising:

• an array of memory cells including a plurality of sectors;
• a decoder, responsive to memory addresses, to access memory cells in the plurality of sectors;
• and
• programmable circuitry to configure the decoder so that a subset including one or more of the plurality of sectors is disabled and remaining sectors are accessed by sequential addresses;
• and
• wherein the plurality of sectors are identified by an N bit field in a memory address, and the programmable circuitry includes logic which divides the array into a first subset including sectors having a particular p bit subfield of the N bit field at a first value, and a second subset including sectors having the particular p bit subfield of the N bit field different than the first value, and substitutes in the sequential addressing a defective sector in the first subset with a sector in the second subset having at least one of the other N-p bits of the N bit field in common with the defective sector, where p is between 1 and N-1.

An integrated circuit memory, comprising:

• an array of memory cells including a plurality of sectors;
• a decoder, responsive to memory addresses, to access memory cells in the plurality of sectors;
• programmable circuitry to configure the decoder so that a subset including one or more of the plurality of sectors is disabled and remaining sectors are accessed by sequential addresses;
• a plurality of wordline drivers, wordline drivers in the plurality having a first mode which selectively drives a positive voltage or a first mode reference voltage to wordlines in the array, and second mode which selectively drives a negative voltage or a second mode reference voltage to the wordlines;
• and
• logic to prevent the negative voltage from being applied to wordlines in disabled sectors.