Page mode mask ROM using a two-stage latch circuit and a method for controlling the same

A memory device including a cell array storing data comprising:

• an Y-predecoding means for decoding Y-addresses in response to an enable signal which is generated by a count circuit receiving clock signals, said count circuit being reset in response to an address transition pulse;
• an Y-decoding means for reading said data stored in said cell array according to the output from said Y-predecoding means;
• an amplification means for amplifying said data in response to said enable signal;
• and
• a control signal generating means for providing said enable signal with said Y-predecoding means and said amplification means and generating a latch signal;
• at least one latch means including:
• a first latch means for storing said data from said amplification means;
• a second latch means for storing said data from said first latch means;
• and
• a switching means for transferring said data stored in said first latch means to said second latch means in response to said latch signal which is generated by said control signal generating means.