Semiconductor memory having extended data out function
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYoshinori Inoue
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory, bit data read out of a memory cell are placed on a data line pair. The gate control circuit detects the transfer of the bit data to the data line pair and activates the control signal. The active control signal turns on the transfer gates located between the data line pair and the output buffer circuit so that the bit data are transferred and held by the latch circuits. The output buffer circuit releases output data represented by the latched bit data to the outside by way of the data input/output pin. This arrangement and operation eliminate the floating state of external output data and extend the duration of valid external output data in one operation cycle.
Claims13
A semiconductor memory comprising:
- a memory cell array including a plurality of memory cells for storing bit data;
- a data line which carries the bit data read out from a memory cell of said memory cell array;
- gate control means configured for detecting, at the time of data readout, that the bit data from said memory cell array is placed on said data line, and in response generating a control signal;
- gate means configured for receiving said control signal, and in response transferring the bit data placed on said data line;
- latch means configured for receiving and holding the bit data from said gate means;
- and
- output buffer means which outputs data represented by the bit data held in said latch means.
A semiconductor memory capable of testing a plurality of bits concurrently, said memory comprising:
- a memory cell array including a plurality of memory cells for storing bit data;
- first logic gate means which, at the time of testing, receives multiple bit data of a first polarity out of bit data pairs read out simultaneously from the memory cells in which same bit data has been stored, and produces first data indicative of an exclusive negative logical product of said multiple bit data of the first polarity;
- second logic gate means which, at the time of testing, receives multiple bit data of a second polarity out of bit data pairs read out simultaneously from said memory cells, and produces second data indicative of an exclusive logical product of said multiple bit data of the second polarity;
- a data line which carries the first and second data produced by said first and second logic gate means;
- gate control means configured for detecting, at the time of testing, that said first and second data are placed on said data line, and in response generating a control signal;
- gate means configured for receiving said control signal, and in response transferring the first and second data placed on said data line;
- latch means configured for receiving and holding the first and second data from said gate means;
- and
- output buffer means which outputs data represented by the first and second data held in said latch means.
Dependencies are inferred from the claim text.